Message ID | 1528198148-23308-2-git-send-email-michel.pollet@bp.renesas.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Simon Horman |
Headers | show |
On Tue, Jun 5, 2018 at 1:28 PM, Michel Pollet <michel.pollet@bp.renesas.com> wrote: > Add a special enable method for second CA7 of the R9A06G032 > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
On Tue, Jun 05, 2018 at 12:28:46PM +0100, Michel Pollet wrote: > Add a special enable method for second CA7 of the R9A06G032 > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 29e1dc5..b395d107 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -219,6 +219,7 @@ described below. "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" "renesas,apmu" + "renesas,r9a06g032-smp" "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp"