From patchwork Tue Jun 5 11:28:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michel Pollet X-Patchwork-Id: 10448073 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DA50460467 for ; Tue, 5 Jun 2018 11:34:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C892129129 for ; Tue, 5 Jun 2018 11:34:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD00829127; Tue, 5 Jun 2018 11:34:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 66BA529129 for ; Tue, 5 Jun 2018 11:34:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751726AbeFELej (ORCPT ); Tue, 5 Jun 2018 07:34:39 -0400 Received: from relmlor4.renesas.com ([210.160.252.174]:58304 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751534AbeFELei (ORCPT ); Tue, 5 Jun 2018 07:34:38 -0400 Received: from unknown (HELO relmlir4.idc.renesas.com) ([10.200.68.154]) by relmlie3.idc.renesas.com with ESMTP; 05 Jun 2018 20:34:37 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir4.idc.renesas.com (Postfix) with ESMTP id 2E9A2836C1; Tue, 5 Jun 2018 20:34:37 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.49,478,1520866800"; d="scan'208";a="283089225" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 05 Jun 2018 20:34:32 +0900 From: Michel Pollet To: linux-renesas-soc@vger.kernel.org, Simon Horman Cc: phil.edworthy@renesas.com, Michel Pollet , Michel Pollet , Rob Herring , Mark Rutland , Magnus Damm , Russell King , Florian Fainelli , Chen-Yu Tsai , Douglas Anderson , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rajendra Nayak , Stefan Wahren , Frank Rowand , Carlo Caione , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver Date: Tue, 5 Jun 2018 12:28:47 +0100 Message-Id: <1528198148-23308-3-git-send-email-michel.pollet@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528198148-23308-1-git-send-email-michel.pollet@bp.renesas.com> References: <1528198148-23308-1-git-send-email-michel.pollet@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it requires a special enable method to get it started. Signed-off-by: Michel Pollet Reviewed-by: Geert Uytterhoeven --- arch/arm/mach-shmobile/Makefile | 1 + arch/arm/mach-shmobile/smp-r9a06g032.c | 79 ++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 1939f52..d7fc98f 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -34,6 +34,7 @@ smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o smp-$(CONFIG_ARCH_R8A7790) += smp-r8a7790.o smp-$(CONFIG_ARCH_R8A7791) += smp-r8a7791.o +smp-$(CONFIG_ARCH_R9A06G032) += smp-r9a06g032.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o # PM objects diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c b/arch/arm/mach-shmobile/smp-r9a06g032.c new file mode 100644 index 0000000..cd40e6e --- /dev/null +++ b/arch/arm/mach-shmobile/smp-r9a06g032.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R9A06G032 Second CA7 enabler. + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet , + * Derived from action,s500-smp + */ + +#include +#include +#include +#include + +/* + * The second CPU is parked in ROM at boot time. It requires waking it after + * writing an address into the BOOTADDR register of sysctrl. + * + * So the default value of the "cpu-release-addr" corresponds to BOOTADDR... + * + * *However* the BOOTADDR register is not available when the kernel + * starts in NONSEC mode. + * + * So for NONSEC mode, the bootloader re-parks the second CPU into a pen + * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address, + * which is not restricted. + */ + +static void __iomem *cpu_bootaddr; + +static DEFINE_SPINLOCK(cpu_lock); + +static int r9a06g032_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + if (!cpu_bootaddr) + return -ENODEV; + + spin_lock(&cpu_lock); + + writel(__pa_symbol(secondary_startup), cpu_bootaddr); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + spin_unlock(&cpu_lock); + + return 0; +} + +static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *dn; + int ret; + u32 bootaddr; + + dn = of_get_cpu_node(1, NULL); + if (!dn) { + pr_err("CPU#1: missing device tree node\n"); + return; + } + /* + * Determine the address from which the CPU is polling. + * The bootloader *does* change this property + */ + ret = of_property_read_u32(dn, "cpu-release-addr", &bootaddr); + of_node_put(dn); + if (ret) { + pr_err("CPU#1: invalid cpu-release-addr property\n"); + return; + } + pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr); + + cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr)); +} + +static const struct smp_operations r9a06g032_smp_ops __initconst = { + .smp_prepare_cpus = r9a06g032_smp_prepare_cpus, + .smp_boot_secondary = r9a06g032_smp_boot_secondary, +}; +CPU_METHOD_OF_DECLARE(r9a06g032_smp, "renesas,r9a06g032-smp", &r9a06g032_smp_ops);