From patchwork Fri Jun 8 16:19:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 10454695 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A103E60159 for ; Fri, 8 Jun 2018 16:24:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 852D4292CA for ; Fri, 8 Jun 2018 16:24:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 79940292DC; Fri, 8 Jun 2018 16:24:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 92FD5292CA for ; Fri, 8 Jun 2018 16:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751524AbeFHQYX (ORCPT ); Fri, 8 Jun 2018 12:24:23 -0400 Received: from relmlor3.renesas.com ([210.160.252.173]:27543 "EHLO relmlie2.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751141AbeFHQYW (ORCPT ); Fri, 8 Jun 2018 12:24:22 -0400 Received: from unknown (HELO relmlir1.idc.renesas.com) ([10.200.68.151]) by relmlie2.idc.renesas.com with ESMTP; 09 Jun 2018 01:24:21 +0900 Received: from relmlii2.idc.renesas.com (relmlii2.idc.renesas.com [10.200.68.66]) by relmlir1.idc.renesas.com (Postfix) with ESMTP id A970A42923; Sat, 9 Jun 2018 01:24:21 +0900 (JST) X-IronPort-AV: E=Sophos;i="5.49,490,1520866800"; d="scan'208";a="283476141" Received: from unknown (HELO be1yocto.ree.adwin.renesas.com) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 09 Jun 2018 01:24:18 +0900 From: Biju Das To: Daniel Lezcano , Thomas Gleixner Cc: Simon Horman , Geert Uytterhoeven , Chris Paterson , Fabrizio Castro , linux-renesas-soc@vger.kernel.org, Biju Das Subject: [PATCH] clocksource/drivers/sh_cmt: wait for CMCNT on init Date: Fri, 8 Jun 2018 17:19:45 +0100 Message-Id: <1528474785-11778-1-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As per section 57A.3.5/69A.3.5/79.A.3.5 of rz/g/r-car gen2/3 hardware manual,it is mentioned that we need to provide 2 cycles in counter input clock (RCLK) for reflecting written data to counter behaviour. Adding sufficient wait to let the CMCNT register value settle before starting the timer channel. It fixes the error "sh_cmt ffca0000.timer: ch1: cannot clear CMCNT" Signed-off-by: Biju Das Reviewed-by: Chris Paterson --- Hello, During cmt testing, the tool (tools/testing/selftests/timers/clocksource-switch.c) is complaining about the error "sh_cmt ffca0000.timer: ch1: cannot clear CMCNT". The above patch fixes this issue is by adding sufficient wait to let the CMCNT register value settle before starting the timer channel. This issue is reproduced on Koelsch/RZ/G1[ME] based iwave boards etc..., as I assume the same issue should be present on lager etc. as well? regards, Biju drivers/clocksource/sh_cmt.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index 70b3cf8..48910df 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -328,7 +328,7 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start) static int sh_cmt_enable(struct sh_cmt_channel *ch) { - int k, ret; + int j, k, ret; pm_runtime_get_sync(&ch->cmt->pdev->dev); dev_pm_syscore_device(&ch->cmt->pdev->dev, true); @@ -368,11 +368,17 @@ static int sh_cmt_enable(struct sh_cmt_channel *ch) * While at it, we're supposed to clear out the CMCNT as of this * moment, so make sure it's processed properly here. This will * take RCLKx2 at maximum. + * + * Similar register access usage for CMCNT is mentioned in R-Car + * Gen[2/3]/RZ/G1 user's manual, RCLKx2 for cmt0 and RCLKx2 or + * CPϕx2 (CPEXϕx2)) for cmt1. */ - for (k = 0; k < 100; k++) { - if (!sh_cmt_read_cmcnt(ch)) - break; - udelay(1); + for (j = 0; j < 2; j++) { + for (k = 0; k < 100; k++) { + if (!sh_cmt_read_cmcnt(ch)) + break; + udelay(1); + } } if (sh_cmt_read_cmcnt(ch)) {