diff mbox

[v9,3/5] ARM: dts: Renesas R9A06G032 base device tree file

Message ID 1528973829-25493-4-git-send-email-michel.pollet@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Simon Horman
Headers show

Commit Message

Michel Pollet June 14, 2018, 10:56 a.m. UTC 
This adds the Renesas R9A06G032 bare bone support.

This currently only handles the SYSCTRL block note,
generic parts (gic, architected timer) and a UART.

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 114 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)
 create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi

Comments

Geert Uytterhoeven June 22, 2018, 12:14 p.m. UTC | #1 
Hi Michel,

CC MarcZ

On Thu, Jun 14, 2018 at 1:02 PM Michel Pollet
<michel.pollet@bp.renesas.com> wrote:
> This adds the Renesas R9A06G032 bare bone support.
>
> This currently only handles the SYSCTRL block note,
> generic parts (gic, architected timer) and a UART.
>
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>

> --- /dev/null
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi

> +       timer {
> +               compatible = "arm,cortex-a7-timer",

Checkpatch says:
WARNING: DT compatible string "arm,cortex-a7-timer" appears
un-documented -- check ./Documentation/devicetree/bindings/

> +                            "arm,armv7-timer";

Documentation/devicetree/bindings/arm/arch_timer.txt says:

    compatible should at least contain "arm,armv7-timer"

but fails to list other possible values?

> +               interrupt-parent = <&gic>;
> +               arm,cpu-registers-not-fw-configured;
> +               always-on;
> +               interrupts =
> +                       <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> +       };

Gr{oetje,eeting}s,

                        Geert
Marc Zyngier June 22, 2018, 12:25 p.m. UTC | #2 
On 22/06/18 13:14, Geert Uytterhoeven wrote:
> Hi Michel,
> 
> CC MarcZ
> 
> On Thu, Jun 14, 2018 at 1:02 PM Michel Pollet
> <michel.pollet@bp.renesas.com> wrote:
>> This adds the Renesas R9A06G032 bare bone support.
>>
>> This currently only handles the SYSCTRL block note,
>> generic parts (gic, architected timer) and a UART.
>>
>> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> 
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> 
>> +       timer {
>> +               compatible = "arm,cortex-a7-timer",
> 
> Checkpatch says:
> WARNING: DT compatible string "arm,cortex-a7-timer" appears
> un-documented -- check ./Documentation/devicetree/bindings/
> 
>> +                            "arm,armv7-timer";
> 
> Documentation/devicetree/bindings/arm/arch_timer.txt says:
> 
>     compatible should at least contain "arm,armv7-timer"
> 
> but fails to list other possible values?

The idea is that you could add something useful that matches your CPU.
Adding new CPU types in the binding seems to be a never ending battle...

> 
>> +               interrupt-parent = <&gic>;
>> +               arm,cpu-registers-not-fw-configured;

Really? :-(

Thanks,

	M.
diff mbox

Patch

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
new file mode 100644
index 0000000..353e06f
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -0,0 +1,114 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+/ {
+	compatible = "renesas,r9a06g032";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0>;
+			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <1>;
+			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+		};
+	};
+
+	ext_jtag_clk: extjtagclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	ext_mclk: extmclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <40000000>;
+	};
+
+	ext_rgmii_ref: extrgmiiref {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	ext_rtc_clk: extrtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-parent = <&gic>;
+		ranges;
+
+		sysctrl: system-controller@4000c000 {
+			compatible = "renesas,r9a06g032-sysctrl";
+			reg = <0x4000c000 0x1000>;
+			status = "okay";
+			#clock-cells = <1>;
+
+			clocks = <&ext_mclk>, <&ext_rtc_clk>,
+					<&ext_jtag_clk>, <&ext_rgmii_ref>;
+			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+		};
+
+		uart0: serial@40060000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x40060000 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&sysctrl R9A06G032_CLK_UART0>;
+			clock-names = "baudclk";
+			status = "disabled";
+		};
+
+		gic: gic@44101000 {
+			compatible = "arm,cortex-a7-gic", "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x44101000 0x1000>, /* Distributer */
+			      <0x44102000 0x2000>, /* CPU interface */
+			      <0x44104000 0x2000>, /* Virt interface control */
+			      <0x44106000 0x2000>; /* Virt CPU interface */
+			interrupts =
+				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+
+	timer {
+		compatible = "arm,cortex-a7-timer",
+			     "arm,armv7-timer";
+		interrupt-parent = <&gic>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+		interrupts =
+			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};