| Message ID | 1529915110-5867-3-git-send-email-michel.pollet@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Michel, On Mon, Jun 25, 2018 at 10:31 AM Michel Pollet <michel.pollet@bp.renesas.com> wrote: > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it > requires a special enable method to get it started. > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > arch/arm/mach-shmobile/Makefile | 1 + > arch/arm/mach-shmobile/smp-r9a06g032.c | 96 ++++++++++++++++++++++++++++++++++ > 2 files changed, 97 insertions(+) > create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c Given this doesn't depend on anything under arch/arm/mach-shmobile/, perhaps this should be moved to drivers/soc/renesas/ (and renamed to r9a06g032-smp.c for consistency) instead? Simon: what do you think? Gr{oetje,eeting}s, Geert
On Mon, Jun 25, 2018 at 11:24:48AM +0200, Geert Uytterhoeven wrote: > Hi Michel, > > On Mon, Jun 25, 2018 at 10:31 AM Michel Pollet > <michel.pollet@bp.renesas.com> wrote: > > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time, it > > requires a special enable method to get it started. > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- > > arch/arm/mach-shmobile/Makefile | 1 + > > arch/arm/mach-shmobile/smp-r9a06g032.c | 96 ++++++++++++++++++++++++++++++++++ > > 2 files changed, 97 insertions(+) > > create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c > > Given this doesn't depend on anything under arch/arm/mach-shmobile/, > perhaps this should be moved to drivers/soc/renesas/ (and renamed to > r9a06g032-smp.c for consistency) instead? > > Simon: what do you think? Yes, I think that would be nice.
On 25 June 2018 10:43, Simon wrote: > > On Mon, Jun 25, 2018 at 11:24:48AM +0200, Geert Uytterhoeven wrote: > > Hi Michel, > > > > On Mon, Jun 25, 2018 at 10:31 AM Michel Pollet > > <michel.pollet@bp.renesas.com> wrote: > > > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot > > > time, it requires a special enable method to get it started. > > > > > > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > > --- > > > arch/arm/mach-shmobile/Makefile | 1 + > > > arch/arm/mach-shmobile/smp-r9a06g032.c | 96 > > > ++++++++++++++++++++++++++++++++++ > > > 2 files changed, 97 insertions(+) > > > create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c > > > > Given this doesn't depend on anything under arch/arm/mach-shmobile/, > > perhaps this should be moved to drivers/soc/renesas/ (and renamed to > > r9a06g032-smp.c for consistency) instead? > > > > Simon: what do you think? > > Yes, I think that would be nice. So, do you guys want me to try to integrate this with the subsystem there, with The renesas-soc bits, or should I just plonk the driver in and change the makefile? Secondary question: is it to for me to repost with these changes ASAP? Cheers Michel Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 05ba728..d24d9c9 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_R8A7793) += regulator-quirk-rcar-gen2.o smp-y := $(cpu-y) smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o +smp-$(CONFIG_ARCH_R9A06G032) += smp-r9a06g032.o smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o # PM objects diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c b/arch/arm/mach-shmobile/smp-r9a06g032.c new file mode 100644 index 0000000..a1926e8 --- /dev/null +++ b/arch/arm/mach-shmobile/smp-r9a06g032.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R9A06G032 Second CA7 enabler. + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com> + * Derived from actions,s500-smp + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/smp.h> + +/* + * The second CPU is parked in ROM at boot time. It requires waking it after + * writing an address into the BOOTADDR register of sysctrl. + * + * So the default value of the "cpu-release-addr" corresponds to BOOTADDR... + * + * *However* the BOOTADDR register is not available when the kernel + * starts in NONSEC mode. + * + * So for NONSEC mode, the bootloader re-parks the second CPU into a pen + * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address, + * which is not restricted. + */ + +static void __iomem *cpu_bootaddr; + +static DEFINE_SPINLOCK(cpu_lock); + +static int +r9a06g032_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + if (!cpu_bootaddr) + return -ENODEV; + + spin_lock(&cpu_lock); + + writel(__pa_symbol(secondary_startup), cpu_bootaddr); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + + spin_unlock(&cpu_lock); + + return 0; +} + +static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *dn; + int ret = -EINVAL, dns; + u32 bootaddr; + + dn = of_get_cpu_node(1, NULL); + if (!dn) { + pr_err("CPU#1: missing device tree node\n"); + return; + } + /* + * Determine the address from which the CPU is polling. + * The bootloader *does* change this property. + * Note: The property can be either 64 or 32 bits, so handle both cases + */ + if (of_find_property(dn, "cpu-release-addr", &dns)) { + if (dns == sizeof(u64)) { + u64 temp; + + ret = of_property_read_u64(dn, + "cpu-release-addr", &temp); + bootaddr = temp; + } else { + ret = of_property_read_u32(dn, + "cpu-release-addr", + &bootaddr); + } + } + of_node_put(dn); + if (ret) { + pr_err("CPU#1: invalid cpu-release-addr property\n"); + return; + } + pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr); + + cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr)); +} + +static const struct smp_operations r9a06g032_smp_ops __initconst = { + .smp_prepare_cpus = r9a06g032_smp_prepare_cpus, + .smp_boot_secondary = r9a06g032_smp_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(r9a06g032_smp, + "renesas,r9a06g032-smp", &r9a06g032_smp_ops);