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[v7,1/3] dt-bindings: cpu: Add Renesas R9A06G032 SMP enable method.

Message ID 1530173842-56851-2-git-send-email-michel.pollet@bp.renesas.com (mailing list archive)
State Accepted
Commit a7eaad7f7517ba7cdabfeb28fa05bae4e70b4b5a
Delegated to: Simon Horman
Headers show

Commit Message

Michel Pollet June 28, 2018, 8:17 a.m. UTC 
Add a special enable method for second CA7 of the R9A06G032

Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

Comments

Simon Horman June 28, 2018, 12:16 p.m. UTC | #1 
On Thu, Jun 28, 2018 at 09:17:12AM +0100, Michel Pollet wrote:
> Add a special enable method for second CA7 of the R9A06G032
> 
> Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Thanks, applied.
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 29e1dc5..b395d107 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -219,6 +219,7 @@  described below.
 			    "qcom,kpss-acc-v1"
 			    "qcom,kpss-acc-v2"
 			    "renesas,apmu"
+			    "renesas,r9a06g032-smp"
 			    "rockchip,rk3036-smp"
 			    "rockchip,rk3066-smp"
 			    "ste,dbx500-smp"