diff mbox series

[2/3] drm: rcar-du: Write ESCR register per channel

Message ID 1534922509-15197-3-git-send-email-jacopo+renesas@jmondi.org (mailing list archive)
State Under Review
Delegated to: Geert Uytterhoeven
Headers show
Series drm: rcar-du: A few cosmetic changes | expand

Commit Message

Jacopo Mondi Aug. 22, 2018, 7:21 a.m. UTC
The ESCR registers offset definition is confusing, as each channel is
equipped with an ESCR register instance, but the names suggest only ESCR and
ESCR2 are taken into account.

Rename the offsets to a name that includes the channels they apply to, and
write them to each channel with 'rcar_du_crtc_write()'.

Cosmetic patch, no functional changes intended.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +--
 drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
 2 files changed, 3 insertions(+), 4 deletions(-)

Comments

Laurent Pinchart Aug. 22, 2018, 12:17 p.m. UTC | #1
Hi Jacopo,

Thank you for the patch.

On Wednesday, 22 August 2018 10:21:48 EEST Jacopo Mondi wrote:
> The ESCR registers offset definition is confusing, as each channel is
> equipped with an ESCR register instance, but the names suggest only ESCR and
> ESCR2 are taken into account.
> 
> Rename the offsets to a name that includes the channels they apply to, and
> write them to each channel with 'rcar_du_crtc_write()'.
> 
> Cosmetic patch, no functional changes intended.

I think patches 2/3 and 3/3 can be squashed together, there's no real reason 
to keep them separate. I propose updating the commit message to

"drm: rcar-du: Write ESCR and OTAR as CRTC registers 
  
The ESCR and OTAR registers exist in each DU channel, but at different 
offsets for odd and even channels. This led to usage of the group 
register access API to write them, with offsets macros named ESCR/OTAR 
and ESCR2/OTAR2 for the first and second ESCR/OTAR register in the group 
respectively.

The names are confusing as it suggests that the ESCR/OTAR registers for 
DU0 and DU2 are taken into account, especially with writes performed to
the group register access API.

Rename the offsets to ESCR/OTAR02 and ESCR/OTAR13, and use the CRTC 
register access API to clarify the code. The offsets values are updated 
accordingly.

Cosmetic patch, no functional changes intended."

Otherwise the patches look good to me, so

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

and applied the squashed version to my tree.

> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +--
>  drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
>  2 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 5454884..714c1fc 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -294,8 +294,7 @@ static void rcar_du_crtc_set_display_timing(struct
> rcar_du_crtc *rcrtc) }
>  	}
> 
> -	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
> -			    escr);
> +	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
>  	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
> 
>  	/* Signal polarities */
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index 9dfd220..ebc4aea 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> @@ -492,8 +492,8 @@
>   * External Synchronization Control Registers
>   */
> 
> -#define ESCR			0x10000
> -#define ESCR2			0x31000
> +#define ESCR02			0x10000
> +#define ESCR13			0x01000
>  #define ESCR_DCLKOINV		(1 << 25)
>  #define ESCR_DCLKSEL_DCLKIN	(0 << 20)
>  #define ESCR_DCLKSEL_CLKS	(1 << 20)
Kieran Bingham Aug. 30, 2018, 4 p.m. UTC | #2
Hi Jacopo,

On 22/08/18 08:21, Jacopo Mondi wrote:
> The ESCR registers offset definition is confusing, as each channel is
> equipped with an ESCR register instance, but the names suggest only ESCR and
> ESCR2 are taken into account.
> 
> Rename the offsets to a name that includes the channels they apply to, and
> write them to each channel with 'rcar_du_crtc_write()'.
> 
> Cosmetic patch, no functional changes intended.

Noted, ...

> 
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +--
>  drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
>  2 files changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 5454884..714c1fc 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -294,8 +294,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>  		}
>  	}
>  
> -	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
> -			    escr);
> +	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
>  	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
>  
>  	/* Signal polarities */
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> index 9dfd220..ebc4aea 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
> @@ -492,8 +492,8 @@
>   * External Synchronization Control Registers
>   */
>  
> -#define ESCR			0x10000
> -#define ESCR2			0x31000
> +#define ESCR02			0x10000
> +#define ESCR13			0x01000

Assertion failed at:
 ASSERT(ESCR2 == ESCR13)

This looks intentional ?
but that makes this a bit more than a cosmetic change?




>  #define ESCR_DCLKOINV		(1 << 25)
>  #define ESCR_DCLKSEL_DCLKIN	(0 << 20)
>  #define ESCR_DCLKSEL_CLKS	(1 << 20)
>
Kieran Bingham Aug. 30, 2018, 4:12 p.m. UTC | #3
Hi Jacopo,

On 30/08/18 17:00, Kieran Bingham wrote:
> Hi Jacopo,
> 
> On 22/08/18 08:21, Jacopo Mondi wrote:
>> The ESCR registers offset definition is confusing, as each channel is
>> equipped with an ESCR register instance, but the names suggest only ESCR and
>> ESCR2 are taken into account.
>>
>> Rename the offsets to a name that includes the channels they apply to, and
>> write them to each channel with 'rcar_du_crtc_write()'.
>>
>> Cosmetic patch, no functional changes intended.
> 
> Noted, ...
> 
>>
>> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>> ---
>>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 3 +--
>>  drivers/gpu/drm/rcar-du/rcar_du_regs.h | 4 ++--
>>  2 files changed, 3 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> index 5454884..714c1fc 100644
>> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
>> @@ -294,8 +294,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>>  		}
>>  	}
>>  
>> -	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
>> -			    escr);
>> +	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);

>>  	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
>>  
>>  	/* Signal polarities */
>> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
>> index 9dfd220..ebc4aea 100644
>> --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
>> +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
>> @@ -492,8 +492,8 @@
>>   * External Synchronization Control Registers
>>   */
>>  
>> -#define ESCR			0x10000
>> -#define ESCR2			0x31000
>> +#define ESCR02			0x10000
>> +#define ESCR13			0x01000
> 
> Assertion failed at:
>  ASSERT(ESCR2 == ESCR13)
> 
> This looks intentional ?
> but that makes this a bit more than a cosmetic change?

Aha - sorry - I see.

It looks like the '0x3' from '0x31000' was providing the offset into the
group I assume.


I'm surprised an equivalent offset wasn't removed from the ESCR02.

But I assume this is handled by the change of "rcar_du_crtc_write() ->
rcar_du_group_write()"?

Regards

Kieran



> 
> 
> 
> 
>>  #define ESCR_DCLKOINV		(1 << 25)
>>  #define ESCR_DCLKSEL_DCLKIN	(0 << 20)
>>  #define ESCR_DCLKSEL_CLKS	(1 << 20)
>>
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index 5454884..714c1fc 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -294,8 +294,7 @@  static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
 		}
 	}
 
-	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
-			    escr);
+	rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
 	rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
 
 	/* Signal polarities */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
index 9dfd220..ebc4aea 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h
@@ -492,8 +492,8 @@ 
  * External Synchronization Control Registers
  */
 
-#define ESCR			0x10000
-#define ESCR2			0x31000
+#define ESCR02			0x10000
+#define ESCR13			0x01000
 #define ESCR_DCLKOINV		(1 << 25)
 #define ESCR_DCLKSEL_DCLKIN	(0 << 20)
 #define ESCR_DCLKSEL_CLKS	(1 << 20)