From patchwork Thu Aug 23 15:12:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacopo Mondi X-Patchwork-Id: 10574253 X-Patchwork-Delegate: kieran@bingham.xyz Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82CBC13B6 for ; Thu, 23 Aug 2018 15:12:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 60BB32C104 for ; Thu, 23 Aug 2018 15:12:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5468D2C285; Thu, 23 Aug 2018 15:12:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E979D2C104 for ; Thu, 23 Aug 2018 15:12:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732671AbeHWSmi (ORCPT ); Thu, 23 Aug 2018 14:42:38 -0400 Received: from relay4-d.mail.gandi.net ([217.70.183.196]:45903 "EHLO relay4-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732016AbeHWSmi (ORCPT ); Thu, 23 Aug 2018 14:42:38 -0400 X-Originating-IP: 2.224.242.101 Received: from w540.lan (2-224-242-101.ip172.fastwebnet.it [2.224.242.101]) (Authenticated sender: jacopo@jmondi.org) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id E1D6EE0013; Thu, 23 Aug 2018 15:12:30 +0000 (UTC) From: Jacopo Mondi To: Laurent Pinchart , David Airlie Cc: Jacopo Mondi , ulrich.hecht+renesas@gmail.com, kieran.bingham@ideasonboard.com, dri-devel@lists.freedesktop.org (open list:DRM DRIVERS FOR RENESAS), linux-renesas-soc@vger.kernel.org (open list:DRM DRIVERS FOR RENESAS) Subject: [PATCH 3/4] drm: rcar-du: Fix handling of DORCR for group 1 Date: Thu, 23 Aug 2018 17:12:13 +0200 Message-Id: <1535037134-373-4-git-send-email-jacopo+renesas@jmondi.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> References: <1535037134-373-1-git-send-email-jacopo+renesas@jmondi.org> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to revision 1.00 of R-Car Gen3 Soc manual, only DU channels of group 0 (DU0 and DU1) supports output control routing through register DORCR0. For channels of group 1 (DU2 and DU3) which are only present on H3/M3-W/M3-N SoCs, no routing options are available between super-imposition processors and the output pin controller. The updated version of the SoC manual prescribes thus to hardcode DPRCR2 bits that controls output pin routing for those channels. Signed-off-by: Jacopo Mondi --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index ef2c177..e79d424 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -127,10 +127,19 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10); /* - * Use DS1PR and DS2PR to configure planes priorities and connects the - * superposition 0 to DU0 pins. DU1 pins will be configured dynamically. + * For group 0 (DU0/DU1) use DS1PR and DS2PR to configure planes + * priorities and connects the superposition 0 to DU0 pins. + * DU1 pins will be configured dynamically. + * + * For group 1 (DU2/DU3), if any, use DS2PR and DS3PT to configure + * planes priorities and hardcode other bits. */ - rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); + if (rgrp->index == 0) + rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS); + else + rcar_du_group_write(rgrp, DORCR, DORCR_PG2T | DORCR_DK2S | + DORCR_PG2D_DS2 | DORCR_DPRS); + /* Apply planes to CRTCs association. */ mutex_lock(&rgrp->lock); @@ -247,6 +256,10 @@ int rcar_du_group_set_routing(struct rcar_du_group *rgrp) struct rcar_du_crtc *crtc0 = &rgrp->dev->crtcs[rgrp->index * 2]; u32 dorcr = rcar_du_group_read(rgrp, DORCR); + /* Only group 0 (DU0/DU1) has pin routing options. */ + if (rgrp->index > 0) + return 0; + dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK); /*