diff mbox series

[2/2] clk: renesas: r8a77965: Add FDP clock

Message ID 1535086349-10657-3-git-send-email-na-hoan@jinso.co.jp (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series Add support fdp1 device for Salvator-XS M3-N | expand

Commit Message

グェン・アン・ホァン Aug. 24, 2018, 4:52 a.m. UTC 
From: Hoan Nguyen An <na-hoan@jinso.co.jp>

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
---
 drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Laurent Pinchart Aug. 24, 2018, 8:54 a.m. UTC | #1 
Hello Nguyen An,

Thank you for the patch.

On Friday, 24 August 2018 07:52:29 EEST Nguyen An Hoan wrote:
> From: Hoan Nguyen An <na-hoan@jinso.co.jp>

Here too a commit message would be nice.

> Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
> ---
>  drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 312f9fe..d0847dc 100644
> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[]
> __initconst = { };
> 
>  static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> +	DEF_MOD("fdp0",			119,	R8A77965_CLK_S0D1),

I haven't found information in the datasheet to confirm whether the parent 
clock is correct. As it doesn't matter too much given that the parent clock 
doesn't need to be controlled, and the FDP driver doesn't care about the clock 
frequency, we can start with this without any problem.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  	DEF_MOD("scif5",		202,	R8A77965_CLK_S3D4),
>  	DEF_MOD("scif4",		203,	R8A77965_CLK_S3D4),
>  	DEF_MOD("scif3",		204,	R8A77965_CLK_S3D4),
Geert Uytterhoeven Aug. 28, 2018, 9:05 a.m. UTC | #2 
Hi Hoan,

On Fri, Aug 24, 2018 at 6:52 AM Nguyen An Hoan <na-hoan@jinso.co.jp> wrote:
> From: Hoan Nguyen An <na-hoan@jinso.co.jp>
>
> Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
> @@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
>  };
>
>  static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
> +       DEF_MOD("fdp0",                 119,    R8A77965_CLK_S0D1),

In the datasheet, and in drivers for other SoCs, this clock is called fdp1-0.

>         DEF_MOD("scif5",                202,    R8A77965_CLK_S3D4),
>         DEF_MOD("scif4",                203,    R8A77965_CLK_S3D4),
>         DEF_MOD("scif3",                204,    R8A77965_CLK_S3D4),

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Will queue in clk-renesas-for-v4.20, with the clock name fixed, and a commit
message added (stolen from the r8a7796 commit ;-).

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 312f9fe..d0847dc 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -112,6 +112,7 @@  static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+	DEF_MOD("fdp0",			119,	R8A77965_CLK_S0D1),
 	DEF_MOD("scif5",		202,	R8A77965_CLK_S3D4),
 	DEF_MOD("scif4",		203,	R8A77965_CLK_S3D4),
 	DEF_MOD("scif3",		204,	R8A77965_CLK_S3D4),