diff mbox series

[4/4] clk: renesas: r8a77995: Add ZA2 clock

Message ID 1536308743-29573-5-git-send-email-na-hoan@jinso.co.jp (mailing list archive)
State Changes Requested
Delegated to: Geert Uytterhoeven
Headers show
Series Enable Audio support for the Draak D3 board on r8a77995. | expand

Commit Message

グェン・アン・ホァン Sept. 7, 2018, 8:25 a.m. UTC 
From: Hoan Nguyen An <na-hoan@jinso.co.jp>

Add ZA2 clock support for the R8A77995 SoC

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
---
 drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Geert Uytterhoeven Sept. 7, 2018, 9:40 a.m. UTC | #1 
Hi Hoan,

On Fri, Sep 7, 2018 at 10:26 AM Nguyen An Hoan <na-hoan@jinso.co.jp> wrote:
> From: Hoan Nguyen An <na-hoan@jinso.co.jp>
>
> Add ZA2 clock support for the R8A77995 SoC
>
> Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
> @@ -80,6 +80,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
>
>         /* Core Clock Outputs */
>         DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
> +       DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,    10, 2),

(Why /10 * 2 instead of /5?)

ZA2 is not a fixed divider clock, but controlled through the ZA2 Clock
Control Register.

>         DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
>         DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
>         DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 49e6a0d..bc15daa 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -80,6 +80,7 @@  static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
 
 	/* Core Clock Outputs */
 	DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
+	DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,    10, 2),
 	DEF_FIXED("ztr",       R8A77995_CLK_ZTR,   CLK_PLL1,       6, 1),
 	DEF_FIXED("zt",        R8A77995_CLK_ZT,    CLK_PLL1,       4, 1),
 	DEF_FIXED("zx",        R8A77995_CLK_ZX,    CLK_PLL1,       3, 1),