| Message ID | 1540189854-14726-1-git-send-email-na-hoan@jinso.co.jp (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | drm: rcar-du: Re-update the DSYSR register value for start/stop | expand |
Hello! On 22.10.2018 9:30, Nguyen An Hoan wrote: > From: Hoan Nguyen An <na-hoan@jinso.co.jp> > > From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure known initial value" When you cite an commit, at least 12 digits of SHA1 are needed, and the summary needs to enclosed in (""), no just "". > We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp-> mmio_offset is enough, > the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc leading to > mmio addresses for DSYSR may be different. > > Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> > --- > drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c > index d85f0a1..a5f7eed 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c > @@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp) > > static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) > { > - struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; > - > - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, > - start ? DSYSR_DEN : DSYSR_DRES); The continuation line indentation style used above is different from yours below. would be preferable to keep the existing style... > + rcar_du_group_write(rgrp, DSYSR, > + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) | > + (start ? DSYSR_DEN : DSYSR_DRES)); > } > > void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) MBR, Sergei
Hello Hoan, Thank you for the patch. On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote: > From: Hoan Nguyen An <na-hoan@jinso.co.jp> > > From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure > known initial value" What exact commit are you referring to ? The mainline commit that has this subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296. > We only need to update DSYSR0, DSYSR2 for start/stop. > So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc -> > rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may be > different. Is this fixing an actual problem ? If you look at the code, the line struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; makes sure that we select DU0 or DU2 only, so the register write rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, start ? DSYSR_DEN : DSYSR_DRES); should only access DSYSR0 and DSYSR2. > Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> > --- > drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c > b/drivers/gpu/drm/rcar-du/rcar_du_group.c index d85f0a1..a5f7eed 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c > @@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp) > > static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool > start) { > - struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; > - > - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, > - start ? DSYSR_DEN : DSYSR_DRES); > + rcar_du_group_write(rgrp, DSYSR, > + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) | > + (start ? DSYSR_DEN : DSYSR_DRES)); > } > > void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
Dear Sergei Shtylyov-san On 2018/10/22 17:21, Sergei Shtylyov wrote: > Hello! > > On 22.10.2018 9:30, Nguyen An Hoan wrote: > >> From: Hoan Nguyen An <na-hoan@jinso.co.jp> >> >> From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to >> ensure known initial value" > > When you cite an commit, at least 12 digits of SHA1 are needed, and > the summary needs to enclosed in (""), no just "". > >> We only need to update DSYSR0, DSYSR2 for start/stop. So using rgrp-> >> mmio_offset is enough, >> the change back from rcar_du_crtc -> rcar_du_group -> rcar_du_crtc >> leading to >> mmio addresses for DSYSR may be different. >> >> Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> >> --- >> drivers/gpu/drm/rcar-du/rcar_du_group.c | 7 +++---- >> 1 file changed, 3 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c >> b/drivers/gpu/drm/rcar-du/rcar_du_group.c >> index d85f0a1..a5f7eed 100644 >> --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c >> +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c >> @@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp) >> >> static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, >> bool start) >> { >> - struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; >> - >> - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, >> - start ? DSYSR_DEN : DSYSR_DRES); > > The continuation line indentation style used above is different > from yours below. > would be preferable to keep the existing style... Thank you for the comments, and the notes to me about code rules. I note and improve for the next time, thank you! Hoan. > >> + rcar_du_group_write(rgrp, DSYSR, >> + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | >> DSYSR_DEN)) | >> + (start ? DSYSR_DEN : DSYSR_DRES)); >> } >> >> void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) > > MBR, Sergei > >
Dear Laurent-san Thank you for your reply and comments! On 2018/10/22 20:23, Laurent Pinchart wrote: > Hello Hoan, > > Thank you for the patch. > > On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote: >> From: Hoan Nguyen An <na-hoan@jinso.co.jp> >> >> From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure >> known initial value" > What exact commit are you referring to ? The mainline commit that has this > subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296. Seems I have cited the wrong Commit-ID、it is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296 drm: rcar-du: Cache DSYSR value to ensure known initial value >> We only need to update DSYSR0, DSYSR2 for start/stop. >> So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc -> >> rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may be >> different. > Is this fixing an actual problem ? If you look at the code, the line > > struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; > > makes sure that we select DU0 or DU2 only, so the register write > > rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, > start ? DSYSR_DEN : DSYSR_DRES); > > should only access DSYSR0 and DSYSR2. This seems I think to fix the rcar-du problem with M3N-r8a77965, With M3N-R8a77965 we have DU0, DU1, DU3 So, when Laurent-san divide objetcs into rcar_du_group, rcar_du_crtc. DU0, DU1 -> du_group[0] rgrp-> mmio_offset = DU0_REG_OFFSET DU3->du_group[1] and rgrp-> mmio_offset = DU2_REG_OFFSET, but rcrtc->mmio_offset=DU3_REG_OFFSET (with M3N) M3N-R8a77965 not have DU2, So after the command: struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; So in fact, with M3N we are updating DSYSR3 (In this my TC, this reference to start/stop DU3-RGB) This will not affect H3, since the H3 lines always have enough DU0, DU1,DU2,DU3. Thank you very much ! Hoan.
Hello Hoan, On Tuesday, 23 October 2018 04:01:19 EET Hoan wrote: > On 2018/10/22 20:23, Laurent Pinchart wrote: > > On Monday, 22 October 2018 09:30:54 EEST Nguyen An Hoan wrote: > >> From: Hoan Nguyen An <na-hoan@jinso.co.jp> > >> > >> From previous commit 0521ccb "drm: rcar-du: Cache DSYSR value to ensure > >> > >> known initial value" > > > > What exact commit are you referring to ? The mainline commit that has this > > subject is 9144adc5e5a99577bce0d4ee2ca3615f53b9d296. > > Seems I have cited the wrong Commit-ID、it is > > 9144adc5e5a99577bce0d4ee2ca3615f53b9d296 > drm: rcar-du: Cache DSYSR value to ensure known initial value > > >> We only need to update DSYSR0, DSYSR2 for start/stop. > >> So using rgrp-> mmio_offset is enough, the change back from rcar_du_crtc > >> ->rcar_du_group -> rcar_du_crtc leading to mmio addresses for DSYSR may > >> be different. > > > > Is this fixing an actual problem ? If you look at the code, the line > > > > struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; > > > > makes sure that we select DU0 or DU2 only, so the register write > > > > rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, > > start ? DSYSR_DEN : DSYSR_DRES); > > > > should only access DSYSR0 and DSYSR2. > > This seems I think to fix the rcar-du problem with M3N-r8a77965, > > With M3N-R8a77965 we have DU0, DU1, DU3 > So, when Laurent-san divide objetcs into rcar_du_group, rcar_du_crtc. > > DU0, DU1 -> du_group[0] rgrp-> mmio_offset = DU0_REG_OFFSET > DU3->du_group[1] and rgrp-> mmio_offset = DU2_REG_OFFSET, but > rcrtc->mmio_offset=DU3_REG_OFFSET (with M3N) > > M3N-R8a77965 not have DU2, So after the command: > > struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; > > So in fact, with M3N we are updating DSYSR3 (In this my TC, this > reference to start/stop DU3-RGB) > > This will not affect H3, since the H3 lines always have enough DU0, > DU1,DU2,DU3. You're absolutely right. I'm sorry for introducing the bug in the first place, and for failing to understand your patch. I would however prefer a different fix, as switching back to rcar_du_group_write() defeats the purpose of the "drm: rcar-du: Cache DSYSR value to ensure known initial value" patch. I will submit a patch and CC you.
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index d85f0a1..a5f7eed 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -202,10 +202,9 @@ void rcar_du_group_put(struct rcar_du_group *rgrp) static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start) { - struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2]; - - rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN, - start ? DSYSR_DEN : DSYSR_DRES); + rcar_du_group_write(rgrp, DSYSR, + (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) | + (start ? DSYSR_DEN : DSYSR_DRES)); } void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)