From patchwork Fri Nov 16 07:20:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Hecht X-Patchwork-Id: 10685567 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D49FC14E2 for ; Fri, 16 Nov 2018 07:21:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B995A2D6D2 for ; Fri, 16 Nov 2018 07:21:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE5902D6D6; Fri, 16 Nov 2018 07:21:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C19042D6D2 for ; Fri, 16 Nov 2018 07:21:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389329AbeKPRcl (ORCPT ); Fri, 16 Nov 2018 12:32:41 -0500 Received: from mo4-p01-ob.smtp.rzone.de ([81.169.146.164]:13881 "EHLO mo4-p01-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727451AbeKPRcl (ORCPT ); Fri, 16 Nov 2018 12:32:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; t=1542352889; s=strato-dkim-0002; d=fpond.eu; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: X-RZG-CLASS-ID:X-RZG-AUTH:From:Subject:Sender; bh=sRuQp8tHdsB8fGK/3yLVH4+mYVeM5e3FTB6Ub9lv0KY=; b=ZZw1ttAHVkz+jMOK8CIODEATJzdI8dPsNGm1Fn1YMYE8SItrG46hhCT3LoOdyMA5qF e6ZcKIG7nGICGEpIkajzKQw+CDxbwgQZ8DSbty2jZiBCdo5RQHBvfdsgOet91hTvmvIv KgCmLhvAI9bj7rC5UUXPPvGqhHIcviV1AmYkoH+cADk1PtEVTR5s7PWOjYQ6VxfWHyl3 1KY8f2SCmQDx8fMA3evmceDh5S3sZG/Zs2eeTbjGLF3wH9r4T8CK9+WB5szgrC5Rzgmz pP3FABbl5fzgvyCYsIyieeKTVGvfX4uFCvCcw6q+hQ3THn9vPQ6HYRcNgk/7sJe5YUEv jChQ== X-RZG-AUTH: ":OWANVUa4dPFUgKR/3dpvnYP0Np73dmm4I5W0/AvJ6ahE0tB4eGX21N2+gwi5" X-RZG-CLASS-ID: mo00 Received: from localhost.localdomain by smtp.strato.de (RZmta 44.4 SBL|AUTH) with ESMTPSA id C0291auAG7LK3zN (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (curve secp521r1 with 521 ECDH bits, eq. 15360 bits RSA)) (Client did not present a certificate); Fri, 16 Nov 2018 08:21:20 +0100 (CET) From: Ulrich Hecht To: linux-renesas-soc@vger.kernel.org, geert@linux-m68k.org, wsa@the-dreams.de Cc: Takeshi Kihara , Ulrich Hecht Subject: [PATCH v2 2/4] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions Date: Fri, 16 Nov 2018 15:20:49 +0800 Message-Id: <1542352851-25393-3-git-send-email-uli+renesas@fpond.eu> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542352851-25393-1-git-send-email-uli+renesas@fpond.eu> References: <1542352851-25393-1-git-send-email-uli+renesas@fpond.eu> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. Signed-off-by: Takeshi Kihara Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 95 ++++++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 0af737d..6f3a969 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -550,6 +550,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \ FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \ FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR) +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5) + enum { PINMUX_RESERVED = 0, @@ -575,6 +578,7 @@ enum { PINMUX_IPSR PINMUX_MOD_SELS PINMUX_STATIC + PINMUX_PHYS PINMUX_MARK_END, #undef F_ #undef FM @@ -588,9 +592,6 @@ static const u16 pinmux_data[] = { PINMUX_SINGLE(CLKOUT), PINMUX_SINGLE(HDMI0_CEC), PINMUX_SINGLE(HDMI1_CEC), - PINMUX_SINGLE(I2C_SEL_0_1), - PINMUX_SINGLE(I2C_SEL_3_1), - PINMUX_SINGLE(I2C_SEL_5_1), PINMUX_SINGLE(MSIOF0_RXD), PINMUX_SINGLE(MSIOF0_SCK), PINMUX_SINGLE(MSIOF0_TXD), @@ -614,14 +615,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2), PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), - PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0), - PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), + PINMUX_IPSR_MSEL2(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL2(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL2(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0), + PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0), - PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2), - PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0), + PINMUX_IPSR_MSEL2(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_MSEL2(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_MSEL2(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -674,14 +677,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0), - PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1), - PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1), + PINMUX_IPSR_MSEL2(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_MSEL2(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL2(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_MSEL2(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0), - PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3), - PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1), + PINMUX_IPSR_MSEL2(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_MSEL2(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_MSEL2(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1113,11 +1118,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP), PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), - PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD), - PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), + PINMUX_IPSR_MSEL2(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), - PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP), - PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1), + PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), + PINMUX_IPSR_MSEL2(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1), @@ -2348,6 +2355,15 @@ static const unsigned int hscif4_data_b_mux[] = { }; /* - I2C -------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), +}; + +static const unsigned int i2c0_mux[] = { + SCL0_MARK, SDA0_MARK, +}; + static const unsigned int i2c1_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), @@ -2376,6 +2392,25 @@ static const unsigned int i2c2_b_pins[] = { static const unsigned int i2c2_b_mux[] = { SDA2_B_MARK, SCL2_B_MARK, }; + +static const unsigned int i2c3_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), +}; + +static const unsigned int i2c3_mux[] = { + SCL3_MARK, SDA3_MARK, +}; + +static const unsigned int i2c5_pins[] = { + /* SCL, SDA */ + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), +}; + +static const unsigned int i2c5_mux[] = { + SCL5_MARK, SDA5_MARK, +}; + static const unsigned int i2c6_a_pins[] = { /* SDA, SCL */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), @@ -4258,10 +4293,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(hscif4_clk), SH_PFC_PIN_GROUP(hscif4_ctrl), SH_PFC_PIN_GROUP(hscif4_data_b), + SH_PFC_PIN_GROUP(i2c0), SH_PFC_PIN_GROUP(i2c1_a), SH_PFC_PIN_GROUP(i2c1_b), SH_PFC_PIN_GROUP(i2c2_a), SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c5), SH_PFC_PIN_GROUP(i2c6_a), SH_PFC_PIN_GROUP(i2c6_b), SH_PFC_PIN_GROUP(i2c6_c), @@ -4662,6 +4700,10 @@ static const char * const hscif4_groups[] = { "hscif4_data_b", }; +static const char * const i2c0_groups[] = { + "i2c0", +}; + static const char * const i2c1_groups[] = { "i2c1_a", "i2c1_b", @@ -4672,6 +4714,14 @@ static const char * const i2c2_groups[] = { "i2c2_b", }; +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + static const char * const i2c6_groups[] = { "i2c6_a", "i2c6_b", @@ -5032,8 +5082,11 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(hscif2), SH_PFC_FUNCTION(hscif3), SH_PFC_FUNCTION(hscif4), + SH_PFC_FUNCTION(i2c0), SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c5), SH_PFC_FUNCTION(i2c6), SH_PFC_FUNCTION(intc_ex), SH_PFC_FUNCTION(msiof0),