From patchwork Thu Feb 21 16:10:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gareth Williams X-Patchwork-Id: 10824315 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0343213B5 for ; Thu, 21 Feb 2019 16:11:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E71CD3194C for ; Thu, 21 Feb 2019 16:11:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E578231955; Thu, 21 Feb 2019 16:11:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 787A43194C for ; Thu, 21 Feb 2019 16:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726434AbfBUQLg (ORCPT ); Thu, 21 Feb 2019 11:11:36 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:30900 "EHLO relmlie5.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725880AbfBUQLg (ORCPT ); Thu, 21 Feb 2019 11:11:36 -0500 X-IronPort-AV: E=Sophos;i="5.58,395,1544454000"; d="scan'208";a="8500159" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Feb 2019 01:11:34 +0900 Received: from renesas-VirtualBox.ree.adwin.renesas.com (unknown [10.226.37.56]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C01FC40A6A10; Fri, 22 Feb 2019 01:11:31 +0900 (JST) From: Gareth Williams To: Jarkko Nikula , Andy Shevchenko , Mika Westerberg , linux-i2c@vger.kernel.org Cc: Phil Edworthy , linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Gareth Williams Subject: [PATCH v4 2/2] i2c: designware: Add support for a peripheral clock Date: Thu, 21 Feb 2019 16:10:59 +0000 Message-Id: <1550765459-14519-3-git-send-email-gareth.williams.jx@renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1550765459-14519-1-git-send-email-gareth.williams.jx@renesas.com> References: <1550765459-14519-1-git-send-email-gareth.williams.jx@renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Phil Edworthy The Synopsys I2C Controller has a peripheral clock, but most SoCs hide this away. However, some SoCs need explicit enabling of the peripheral clock in order to access the registers. Therefore, add support for an optional peripheral clock. Signed-off-by: Phil Edworthy Signed-off-by: Gareth Williams Acked-by: Wolfram Sang --- v4: - Updated comments to reference "peripheral clock" instead of "bus clock". - Added Wolfram's Acked-by v3: - busclk renamed to pclk. - Added comment with dw_i2c_dev struct definition describing pclk. - Added enable rollback of first clock if second fails to enable. v2: - Use new devm_clk_get_optional() function as it simplifies handling when the optional clock is not present. --- drivers/i2c/busses/i2c-designware-common.c | 18 ++++++++++++++++-- drivers/i2c/busses/i2c-designware-core.h | 2 ++ drivers/i2c/busses/i2c-designware-platdrv.c | 5 +++++ 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c index a473011..e807aa2 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -251,13 +251,27 @@ unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev) int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare) { + int ret; + if (IS_ERR(dev->clk)) return PTR_ERR(dev->clk); - if (prepare) - return clk_prepare_enable(dev->clk); + if (prepare) { + /* Optional peripheral clock */ + ret = clk_prepare_enable(dev->pclk); + if (ret) + return ret; + + ret = clk_prepare_enable(dev->clk); + if (ret) + clk_disable_unprepare(dev->pclk); + + return ret; + } clk_disable_unprepare(dev->clk); + clk_disable_unprepare(dev->pclk); + return 0; } EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk); diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index b4a0b2b..e88c711 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -177,6 +177,7 @@ * @base: IO registers pointer * @cmd_complete: tx completion indicator * @clk: input reference clock + * @pclk: clock required to access the registers * @slave: represent an I2C slave device * @cmd_err: run time hadware error code * @msgs: points to an array of messages currently being transferred @@ -226,6 +227,7 @@ struct dw_i2c_dev { void __iomem *ext; struct completion cmd_complete; struct clk *clk; + struct clk *pclk; struct reset_control *rst; struct i2c_client *slave; u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev); diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c index 9eaac3b..03fff6a 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -346,6 +346,11 @@ static int dw_i2c_plat_probe(struct platform_device *pdev) else i2c_dw_configure_master(dev); + /* Optional peripheral clock */ + dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk"); + if (IS_ERR(dev->pclk)) + return PTR_ERR(dev->pclk); + dev->clk = devm_clk_get(&pdev->dev, NULL); if (!i2c_dw_prepare_clk(dev, true)) { u64 clk_khz;