From patchwork Wed Jun 12 14:20:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 10990115 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B23BA1395 for ; Wed, 12 Jun 2019 14:25:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2D9D26E40 for ; Wed, 12 Jun 2019 14:25:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 97394287D1; Wed, 12 Jun 2019 14:25:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 39B10287FD for ; Wed, 12 Jun 2019 14:25:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2437345AbfFLOZr (ORCPT ); Wed, 12 Jun 2019 10:25:47 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:57300 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2437334AbfFLOZq (ORCPT ); Wed, 12 Jun 2019 10:25:46 -0400 X-IronPort-AV: E=Sophos;i="5.62,366,1554735600"; d="scan'208";a="18291143" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 12 Jun 2019 23:25:45 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id C0A23400967E; Wed, 12 Jun 2019 23:25:42 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven , Chris Paterson , Fabrizio Castro Subject: [PATCH 2/4] arm64: dts: renesas: r8a774a1: Add CPU capacity-dmips-mhz Date: Wed, 12 Jun 2019 15:20:53 +0100 Message-Id: <1560349255-26336-3-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1560349255-26336-1-git-send-email-biju.das@bp.renesas.com> References: <1560349255-26336-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Set the capacity-dmips-mhz for RZ/G2M(r8a774a1) SoC, that is based on dhrystone. Based on work done by Gaku Inami for r8a7796 SoC. The average dhrystone result for 5 iterations is as below: r8a774a1 SoC (CA57x2 + CA53x4) CPU max-freq dhrystone --------------------------------- CA57 1500 MHz 11428571 lps/s CA53 1200 MHz 5000000 lps/s From this, CPU capacity-dmips-mhz for CA57 and CA53 are calculated as follows: r8a774a1 SoC CA57 : 1024 / (11428571 / 1500) * (11428571 / 1500) = 1024 CA53 : 1024 / (11428571 / 1500) * ( 5000000 / 1200) = 560 Since each CPUs have different max frequencies, the final CPU capacities of A53 scaled by the above difference is as below $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 1024 448 448 448 448 Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index e6ea5a1..603cfdb 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -137,6 +137,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; }; a57_1: cpu@1 { @@ -148,6 +149,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; }; a53_0: cpu@100 { @@ -159,6 +161,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_1: cpu@101 { @@ -170,6 +173,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_2: cpu@102 { @@ -181,6 +185,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; a53_3: cpu@103 { @@ -192,6 +197,7 @@ enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774A1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <560>; }; L2_CA57: cache-controller-0 {