| Message ID | 1567666326-27373-1-git-send-email-biju.das@bp.renesas.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | be67c41781cb4c06a4acb0b92db0cbb728e955e2 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | dt-bindings: power: Add r8a774b1 SYSC power domain definitions | expand |
On Thu, Sep 5, 2019 at 8:58 AM Biju Das <biju.das@bp.renesas.com> wrote: > This patch adds power domain indices for RZ/G2N(a.k.a r8a774b1) SoC. > > Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.5, on a branch to be shared by the SYSC driver and DTS user. Gr{oetje,eeting}s, Geert
diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h new file mode 100644 index 0000000..3737364 --- /dev/null +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774B1_PD_CA57_CPU0 0 +#define R8A774B1_PD_CA57_CPU1 1 +#define R8A774B1_PD_A3VP 9 +#define R8A774B1_PD_CA57_SCU 12 +#define R8A774B1_PD_A3VC 14 +#define R8A774B1_PD_3DG_A 17 +#define R8A774B1_PD_3DG_B 18 +#define R8A774B1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774B1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
This patch adds power domain indices for RZ/G2N(a.k.a r8a774b1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> --- include/dt-bindings/power/r8a774b1-sysc.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 include/dt-bindings/power/r8a774b1-sysc.h