From patchwork Mon Sep 23 14:57:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 11157131 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 66F7D112B for ; Mon, 23 Sep 2019 14:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 45FF920856 for ; Mon, 23 Sep 2019 14:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728018AbfIWO5p (ORCPT ); Mon, 23 Sep 2019 10:57:45 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:25980 "EHLO relmlie6.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726902AbfIWO5o (ORCPT ); Mon, 23 Sep 2019 10:57:44 -0400 X-IronPort-AV: E=Sophos;i="5.64,540,1559487600"; d="scan'208";a="27041343" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 23 Sep 2019 23:57:42 +0900 Received: from be1yocto.ree.adwin.renesas.com (unknown [172.29.43.62]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 566104006196; Mon, 23 Sep 2019 23:57:40 +0900 (JST) From: Biju Das To: Rob Herring , Mark Rutland Cc: Biju Das , Geert Uytterhoeven , Simon Horman , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Fabrizio Castro Subject: [PATCH 1/4] arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices Date: Mon, 23 Sep 2019 15:57:25 +0100 Message-Id: <1569250648-33857-2-git-send-email-biju.das@bp.renesas.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1569250648-33857-1-git-send-email-biju.das@bp.renesas.com> References: <1569250648-33857-1-git-send-email-biju.das@bp.renesas.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org This patch adds OPPs table for CA57{0,1} cpu devices. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f42f646..398bf38 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -45,6 +45,28 @@ clock-frequency = <0>; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -59,6 +81,7 @@ #cooling-cells = <2>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; a57_1: cpu@1 { @@ -69,6 +92,7 @@ next-level-cache = <&L2_CA57>; enable-method = "psci"; clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; }; L2_CA57: cache-controller-0 {