From patchwork Mon Oct 31 19:54:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9406345 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 65C7F60721 for ; Mon, 31 Oct 2016 19:54:07 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5122428E09 for ; Mon, 31 Oct 2016 19:54:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4252D28FA7; Mon, 31 Oct 2016 19:54:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 17FA128E09 for ; Mon, 31 Oct 2016 19:54:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S946157AbcJaTyF (ORCPT ); Mon, 31 Oct 2016 15:54:05 -0400 Received: from mail-lf0-f43.google.com ([209.85.215.43]:32850 "EHLO mail-lf0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S946082AbcJaTyE (ORCPT ); Mon, 31 Oct 2016 15:54:04 -0400 Received: by mail-lf0-f43.google.com with SMTP id c13so5118981lfg.0 for ; Mon, 31 Oct 2016 12:54:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:organization:user-agent :in-reply-to:references:mime-version:content-transfer-encoding; bh=wIwFIdFX6LDEC70t2bvqvIE6YSvzBqGnreSP80tlfM0=; b=lt7bUT7qfswP/UvWqEzv4uklrJoeDaR5XPg71MUIwtZVtmXqTrW8L5AEBPNzKivrvq t+ni/SzAOEvcSaKlRb7o8obPm/uQgmeb6ToQIr+x8xGH10dgfsP/zl/qLlKaAgZek4Bm aXH9vEK8MzglxnwQGzw7HsD0ra8Ao/jXlgRwCeA0Biz5aPM5aZMXdTCsp5KGUkq25Slw fl8LNwgG/oVwFGiCJrHwEVNKu4+NgxfPnLU9C2JTeZ/bawlznuqFd0jEwB2zzt1tz1MR xJkNz9g7njlINtIjEtlcqfERwLbI7Q77iJE2Q6xwzScNOtHiY60vjUvLXIMK25zSiigW xo2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding; bh=wIwFIdFX6LDEC70t2bvqvIE6YSvzBqGnreSP80tlfM0=; b=Uk1OYFh3Pi1+6bG7h/xhhKdI28sJPilWKKcZFn7Zeuv+BJ3uL6NgRKNZnD7YESS7JG UvxJsMMUnJ8CA3Pf9X1sjJy+j4z3yMTGOsAQufxO1BuZORKekqV2gGfadLRrH7BfkZJv n4mywRTyHZbD7xWDDwWkGSgsbOGWoZ8k216n66uBULGQmafn1GqKjqCc7Zh3BqgYaTvW CmjvKhKSv39V74ogd5u/LmzB0AvQlfrmw1dDFc7kmEzT1SyJ13DDIZaAhg0Q84j4hoEG iAsnNXvZv0cIgWGoJ5+G6Zfq8wStUSNDt7vUSIzCi2Vv8qrGf0DhjFxa9QJCqp4qLrVe qLkA== X-Gm-Message-State: ABUngvdzcygu7+p1Z0AtY3cc9gxCuMzAgS6SG/vvp+nyJKCfPBe2EVb0ZkyGI8t/oROePw== X-Received: by 10.25.67.72 with SMTP id m8mr19186213lfj.67.1477943642870; Mon, 31 Oct 2016 12:54:02 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.80.126]) by smtp.gmail.com with ESMTPSA id 89sm4838077lja.42.2016.10.31.12.54.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Oct 2016 12:54:02 -0700 (PDT) From: Sergei Shtylyov To: horms@verge.net.au, linux-renesas-soc@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org Cc: magnus.damm@gmail.com, linux@arm.linux.org.uk, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 1/7] ARM: dts: r8a7743: initial SoC device tree Date: Mon, 31 Oct 2016 22:54:01 +0300 Message-ID: <19450305.ceb133WUUn@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.7.9-100.fc23.x86_64; KDE/4.14.20; x86_64; ; ) In-Reply-To: <1746536.qobnGdHRfV@wasted.cogentembedded.com> References: <1746536.qobnGdHRfV@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The initial R8A7743 SoC device tree including CPU0, GIC, timer, SYSC, RST, CPG, and the required clock descriptions. Based on the original (and large) patch by Dmitry Shifrin . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- Changes in version 6: - corrected the "reg" prop of the RST node; - removed leading zero from the SYSC "reg" property's cell; - fixed the typo in "overriden". Changes in version 5: - added the RST device node, updated the patch description accordingly. Changes in version 4: - removed the CPU1 node, updated the patch description accordingly; - reformatted the "interrupts" props of the GIC/timer device nodes; - added Geert's tag. Changes in version 3: - changed the R8A7743 clock header #include; - replaced the multiple clock nodes with the single CPG node, updated the "clocks" property in the CPU0 node, updated the patch description. Changes in version 2: - added the IRQC and Ether clocks. arch/arm/boot/dts/r8a7743.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7743.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm/boot/dts/r8a7743.dtsi @@ -0,0 +1,120 @@ +/* + * Device Tree Source for the r8a7743 SoC + * + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a7743"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; + power-domains = <&sysc R8A7743_PD_CA15_CPU0>; + next-level-cache = <&L2_CA15>; + }; + + L2_CA15: cache-controller@0 { + compatible = "cache"; + reg = <0>; + cache-unified; + cache-level = <2>; + power-domains = <&sysc R8A7743_PD_CA15_SCU>; + }; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7743-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7743-sysc"; + reg = <0 0xe6180000 0 0x200>; + #power-domain-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7743-rst"; + reg = <0 0xe6160000 0 0x100>; + }; + }; + + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; +};