From patchwork Mon Sep 5 20:17:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9315231 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3C64C60760 for ; Mon, 5 Sep 2016 20:20:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C42B288F8 for ; Mon, 5 Sep 2016 20:20:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2073628900; Mon, 5 Sep 2016 20:20:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84B66288F8 for ; Mon, 5 Sep 2016 20:20:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754711AbcIEUSE (ORCPT ); Mon, 5 Sep 2016 16:18:04 -0400 Received: from mail-lf0-f51.google.com ([209.85.215.51]:33436 "EHLO mail-lf0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754313AbcIEURf (ORCPT ); Mon, 5 Sep 2016 16:17:35 -0400 Received: by mail-lf0-f51.google.com with SMTP id h127so29532786lfh.0 for ; Mon, 05 Sep 2016 13:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:to:subject:date:message-id:organization:user-agent:in-reply-to :references:mime-version:content-transfer-encoding; bh=eMaqmRV60LM3+q98sA07IkfbS9dL2WDoefIk59QiHxY=; b=gDrYJTqtMeSdbYOgyhjCMhJ7winFkFynDvpZ2OQpRBPLi2Le6OTj3/1/YnP4OsIG5c 9l0tJCs3jv28XYN4sOV3PysBItz6iGdkMqOe7B5zhbdNKi+lC/AzuQIQe0id8gSzHaEB adNs61VxWohIzZdRZg8TxeGVokcrRth1P26xqECaOcUnDHGVFihCfe+57vsmla0Gjo2I eaDWRHEAx6guVlSJRsQJAd1cgrJ7sJ9e7jZNx2JTuVdlw7rwV9v0MzeYeMDFwI/z5YrX op2R5V0sF3XBafyzuHhrutgm2QaBTlqjEwBv2AGxq0ID8porxJldClW2GlkPUd/jJbMB wWew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:organization :user-agent:in-reply-to:references:mime-version :content-transfer-encoding; bh=eMaqmRV60LM3+q98sA07IkfbS9dL2WDoefIk59QiHxY=; b=jgOhXISrN1L5S9My1LoWD4pifXtlJFvcXOTkTr4fOn1Wzsjs4vm+bpeLozgfgUzfmx WkyKCGTwi6HoiZ6cMmM0whdt8gNShwU0XH1tv5jEM1yhtDFh9+F9TT/xAeu8O7Mg5V46 XRfHx+MV8WlGxAQJEXyUda6tzPP/CsDWixrB6FZuOrMqtcmlofh0GdFx+NPOlHTUe8H3 msR6YyrbTEg44GC5GP7A24DXmdxQ8WV1mCY/rYCfXhOWVYL+LfT5knOqDbhAA8e7kG+6 mw7MmKe61Q7DI87iYneaR1hXOVJXSBtfUd8uxqdACUlEnfZ/Hi46Tc6Yy+kZEwi+S0xx AOaA== X-Gm-Message-State: AE9vXwO0w1Tsj1zYFGW25EoAyoxCdIMX1+hxNZRKrHTvtlM1v1MK/UZmwOynzYlA3wjurw== X-Received: by 10.46.71.144 with SMTP id u138mr10607515lja.20.1473106653612; Mon, 05 Sep 2016 13:17:33 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.81.57]) by smtp.gmail.com with ESMTPSA id f28sm3561161lji.20.2016.09.05.13.17.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 13:17:32 -0700 (PDT) From: Sergei Shtylyov To: linus.walleij@linaro.org, linux-renesas-soc@vger.kernel.org, laurent.pinchart@ideasonboard.com, linux-gpio@vger.kernel.org, geert+renesas@glider.be Subject: [PATCH] pinctrl: sh-pfc: r8a7792: add MSIOF pin groups Date: Mon, 05 Sep 2016 23:17:31 +0300 Message-ID: <2011444.8BtcIjeJf3@wasted.cogentembedded.com> Organization: Cogent Embedded Inc. User-Agent: KMail/4.14.10 (Linux/4.7.2-101.fc23.x86_64; KDE/4.14.20; x86_64; ; ) In-Reply-To: <1501145.5ro9yfox2Z@wasted.cogentembedded.com> References: <1501145.5ro9yfox2Z@wasted.cogentembedded.com> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- The patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus the QSPI patch last week... drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 82 +++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7792.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1034,6 +1034,64 @@ static const unsigned int lbsc_ex_cs5_pi static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 0), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 1), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 4), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 3), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 5), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 6), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 9), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 8), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -1608,6 +1666,14 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -1734,6 +1800,20 @@ static const char * const lbsc_groups[] "lbsc_ex_cs5", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_rx", + "msiof0_tx", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_rx", + "msiof1_tx", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -1840,6 +1920,8 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3),