From patchwork Wed Feb 17 08:15:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Magnus Damm X-Patchwork-Id: 8335231 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: X-Original-To: patchwork-linux-renesas-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 134CEC02AA for ; Wed, 17 Feb 2016 08:13:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 11DC8202FE for ; Wed, 17 Feb 2016 08:13:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E0475202EC for ; Wed, 17 Feb 2016 08:13:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933782AbcBQIND (ORCPT ); Wed, 17 Feb 2016 03:13:03 -0500 Received: from mail-pa0-f47.google.com ([209.85.220.47]:33397 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932574AbcBQINB (ORCPT ); Wed, 17 Feb 2016 03:13:01 -0500 Received: by mail-pa0-f47.google.com with SMTP id fl4so7324676pad.0; Wed, 17 Feb 2016 00:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:date:message-id:subject; bh=klpcN8SJ78ymYks849PtHk8IU2lYVAlsexS9Oxp8on0=; b=ksn3v/RA7y4lXQBDmn5ox9b4s3SHOe5OSSR2AQ1VIBi+b25Fz6jwLTpBc3I7OzOnQD DLH8iAR3CL07D/JOodNodo4Mr6pVzxc+sBsmsZ6Cy4/KDGwY851LAeNwJCLjpzODH51L ytGP6qV1+Rq4s4FqZmQ8SyjwuGGoD09cmOdpvfkGmXXR74b3twhILgYsSGnK3ftCK927 7odNx4l3mGVhAj12YrWuGVvME5yUMuO0I+lEvEhwtgt/+k395k50ZVkE2B1ClBFl5Wug bsj0GpFVwfiUpMGl/EsbL7if83haMNsqChDZZTL7AEPK0lbB9nxyQpKAhlI3JRdVioAS OR7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:date:message-id:subject; bh=klpcN8SJ78ymYks849PtHk8IU2lYVAlsexS9Oxp8on0=; b=MLOEfAFrTkdfpJs1qzGXsBEgvAJ6yQnu/Cnl0bNRfF975q0KZbNMBSr6hvDfnQVA55 5hbb66HMlrEqkg0FdWj6NTUZXe91+lBHrzdEx+KFvL1c7ykwh468uPZnysXmAif7RvAc E28edYR88cbICAujfy/tUVF1Ypdq26S8ytFAogthnYW3Q5JK53YxfF1grwiY7DcWqtYN 7o29KEmomhE+fm4hxFDBjzsFfx89jaCm3LGIc0SIBNlFYPPpDSpSMstDov67Pu2jfst/ vxSH2tNyt0FEG5MlXL7oxeSerkZ1gwVFpUBLzxB6O7lq+U4YDs+oIY3x8UQFjHeN6H/L qoaQ== X-Gm-Message-State: AG10YORuGiTcv85MuHehN8o9AeicyHnLCO2y673Au551gSeYgaOfg8+5JB83ZvOK3pcekA== X-Received: by 10.66.157.161 with SMTP id wn1mr283502pab.146.1455696780888; Wed, 17 Feb 2016 00:13:00 -0800 (PST) Received: from [127.0.0.1] (s214090.ppp.asahi-net.or.jp. [220.157.214.90]) by smtp.gmail.com with ESMTPSA id 1sm538957pfm.10.2016.02.17.00.12.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Feb 2016 00:12:59 -0800 (PST) From: Magnus Damm To: linux-renesas-soc@vger.kernel.org Cc: linus.walleij@linaro.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, horms@verge.net.au, geert@glider.be, laurent.pinchart@ideasonboard.com, Magnus Damm Date: Wed, 17 Feb 2016 17:15:49 +0900 Message-Id: <20160217081549.17344.77173.sendpatchset@little-apple> Subject: [PATCH v2] pinctrl: sh-pfc: Rework PFC GPIO support Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Magnus Damm The sh-pfc pinctrl driver is currently handling SoC-specific PFC hardware blocks on ARM64, ARM and SH architectures. For older SoCs using SH cores and some 32-bit ARM SoCs the PFC hardware also provides GPIO functionality. On the majority of 32-bit ARM SoCs from Renesas and so far all ARM64 SoCs the GPIO feature is provided by separate hardware blocks. So far GPIO support in the PFC driver has been compiled-in for the majority of the SoCs, but with this patch applied the SoCs with PFC support may select from one of the following: - CONFIG_PINCTRL_SH_PFC - Used if PFC lacks GPIO hardware - CONFIG_PINCTRL_SH_PFC_GPIO - Used if PFC includes GPIO support This patch results in the following changes: - The GPIO functionality is only compiled-in on relevant SoCs - The number of lines of code is reduced Build tested using the following configurations: - r8a7795 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM64) - r8a7790 -> CONFIG_PINCTRL_SH_PFC_GPIO=n -> OK (ARM) - r8a7790 + r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - r8a7740 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (ARM) - sh7751 -> CONFIG_PINCTRL_SH_PFC=n -> OK (SH rts7751r2d1) - sh7724 -> CONFIG_PINCTRL_SH_PFC_GPIO=y -> OK (SH ecovec24) Signed-off-by: Magnus Damm Acked-by: Laurent Pinchart --- Changes since V1: - Simplied Makefile bits to remove sh-pfc-objs and use new Kconfig symbol drivers/pinctrl/sh-pfc/Kconfig | 54 ++++++++++++++------------------------- drivers/pinctrl/sh-pfc/Makefile | 7 +---- drivers/pinctrl/sh-pfc/core.c | 4 +- 3 files changed, 24 insertions(+), 41 deletions(-) --- 0001/drivers/pinctrl/sh-pfc/Kconfig +++ work/drivers/pinctrl/sh-pfc/Kconfig 2016-02-17 16:23:21.630513000 +0900 @@ -5,7 +5,6 @@ if ARCH_SHMOBILE || SUPERH config PINCTRL_SH_PFC - select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB select PINMUX select PINCONF select GENERIC_PINCONF @@ -13,12 +12,12 @@ config PINCTRL_SH_PFC help This enables pin control drivers for SH and SH Mobile platforms -config GPIO_SH_PFC - bool "SuperH PFC GPIO support" - depends on PINCTRL_SH_PFC && GPIOLIB +config PINCTRL_SH_PFC_GPIO + select GPIOLIB + select PINCTRL_SH_PFC + def_bool n help - This enables support for GPIOs within the SoC's pin function - controller. + This enables pin control and GPIO drivers for SH/SH Mobile platforms config PINCTRL_PFC_EMEV2 def_bool y @@ -28,12 +27,12 @@ config PINCTRL_PFC_EMEV2 config PINCTRL_PFC_R8A73A4 def_bool y depends on ARCH_R8A73A4 - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7740 def_bool y depends on ARCH_R8A7740 - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7778 def_bool y @@ -73,79 +72,66 @@ config PINCTRL_PFC_R8A7795 config PINCTRL_PFC_SH7203 def_bool y depends on CPU_SUBTYPE_SH7203 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7264 def_bool y depends on CPU_SUBTYPE_SH7264 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7269 def_bool y depends on CPU_SUBTYPE_SH7269 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH73A0 def_bool y depends on ARCH_SH73A0 - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO select REGULATOR config PINCTRL_PFC_SH7720 def_bool y depends on CPU_SUBTYPE_SH7720 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7722 def_bool y depends on CPU_SUBTYPE_SH7722 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7723 def_bool y depends on CPU_SUBTYPE_SH7723 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7724 def_bool y depends on CPU_SUBTYPE_SH7724 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7734 def_bool y depends on CPU_SUBTYPE_SH7734 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7757 def_bool y depends on CPU_SUBTYPE_SH7757 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7785 def_bool y depends on CPU_SUBTYPE_SH7785 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SH7786 def_bool y depends on CPU_SUBTYPE_SH7786 - depends on GPIOLIB - select PINCTRL_SH_PFC + select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_SHX3 def_bool y depends on CPU_SUBTYPE_SHX3 - depends on GPIOLIB - select PINCTRL_SH_PFC - + select PINCTRL_SH_PFC_GPIO endif --- 0001/drivers/pinctrl/sh-pfc/Makefile +++ work/drivers/pinctrl/sh-pfc/Makefile 2016-02-17 16:26:18.660513000 +0900 @@ -1,8 +1,5 @@ -sh-pfc-objs = core.o pinctrl.o -ifeq ($(CONFIG_GPIO_SH_PFC),y) -sh-pfc-objs += gpio.o -endif -obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o +obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o +obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o --- 0001/drivers/pinctrl/sh-pfc/core.c +++ work/drivers/pinctrl/sh-pfc/core.c 2016-02-17 16:23:21.640513000 +0900 @@ -558,7 +558,7 @@ static int sh_pfc_probe(struct platform_ if (unlikely(ret != 0)) return ret; -#ifdef CONFIG_GPIO_SH_PFC +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO /* * Then the GPIO chip */ @@ -584,7 +584,7 @@ static int sh_pfc_remove(struct platform { struct sh_pfc *pfc = platform_get_drvdata(pdev); -#ifdef CONFIG_GPIO_SH_PFC +#ifdef CONFIG_PINCTRL_SH_PFC_GPIO sh_pfc_unregister_gpiochip(pfc); #endif sh_pfc_unregister_pinctrl(pfc);