From patchwork Thu Nov 17 13:30:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wolfram Sang X-Patchwork-Id: 9434323 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CAFCE60238 for ; Thu, 17 Nov 2016 14:31:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC9D5287A5 for ; Thu, 17 Nov 2016 14:31:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B16E829567; Thu, 17 Nov 2016 14:31:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE6E2287A5 for ; Thu, 17 Nov 2016 14:31:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753405AbcKQObB (ORCPT ); Thu, 17 Nov 2016 09:31:01 -0500 Received: from www.zeus03.de ([194.117.254.33]:56532 "EHLO mail.zeus03.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752043AbcKQOa4 (ORCPT ); Thu, 17 Nov 2016 09:30:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple; d=sang-engineering.com; h= from:to:cc:subject:date:message-id; s=k1; bh=YKiHvHoTZO77+r4ujkA Spcz9vH2ZeW11oTro0q0ozTw=; b=uRz4172FLlA9uxsLlFPuvB1ucNigJkX2UOH bheCNF9NRV4dVzKXUDLnNYDA6Zxr+srzsk4TS0UQpCQctFQ6bQ6pCqrbH8Es0hgf O5WTyr5cCkI8/jDNnbgsrHZKyVAPjXzvHgvBB7jReA08ggMqLflIZ8Vfl4O+Q/2y 6fW9sTfg= Received: (qmail 20513 invoked from network); 17 Nov 2016 14:30:51 +0100 Received: from p5b385fdb.dip0.t-ipconnect.de (HELO localhost) (l3s3148p1@91.56.95.219) by mail.zeus03.de with ESMTPSA (ECDHE-RSA-AES256-GCM-SHA384 encrypted, authenticated); 17 Nov 2016 14:30:51 +0100 From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Geert Uytterhoeven , Simon Horman , linux-gpio@vger.kernel.org, Wolfram Sang Subject: [RFC] pinctrl: sh-pfc: r8a7790: initialize TDSEL register Date: Thu, 17 Nov 2016 14:30:43 +0100 Message-Id: <20161117133043.20771-1-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.10.2 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation says that some bits in TDSEL must be set (ch 5.3.39 in R-Car H2 v0.91). However, the reset value of the register is 0, so software has to do it. Add this to the kernel driver to ensure this is really done independent of firmware versions. This is needed for some SD cards supporting SDR104 transfer mode. For me, TDSEL was not initialized by the firmware and I had problems with the card when re-inserting it. Signed-off-by: Wolfram Sang --- * something like this is needed for all other Gen2 SoCs probably, but I can't test it * I can also only verify the positive result for 'sd0tdsel'. For all other bits, I follow the documentation. Dunno if we better only modify bits we really need? Because of this, patch is still RFC. And values are hardcoded, but seems to be OK with PFC at places, too? * Gen2 has no drive-strength capabilities to play around with, so it must be TDSEL here * Simon: maybe a similar fix helps with the SDR issues you saw on Gose occasionally? drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index b769c05480da68..f01ff6d7052fed 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -24,6 +24,7 @@ #include #include +#include "core.h" #include "sh_pfc.h" /* @@ -5704,7 +5705,16 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return 31 - (pin & 0x1f); } +static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) +{ + /* Initialize TDSEL */ + sh_pfc_write_reg(pfc, 0xe6060088, 32, 0x00155554); + + return 0; +} + static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { + .init = r8a7790_pinmux_soc_init, .pin_to_pocctrl = r8a7790_pin_to_pocctrl, };