From patchwork Tue Jan 17 08:29:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 9520145 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D8C0A6020B for ; Tue, 17 Jan 2017 08:30:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C85C52836B for ; Tue, 17 Jan 2017 08:30:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD47C284FB; Tue, 17 Jan 2017 08:30:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 38048284F6 for ; Tue, 17 Jan 2017 08:29:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750962AbdAQI3Q (ORCPT ); Tue, 17 Jan 2017 03:29:16 -0500 Received: from galahad.ideasonboard.com ([185.26.127.97]:60531 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751008AbdAQI3O (ORCPT ); Tue, 17 Jan 2017 03:29:14 -0500 Received: from avalon.bb.dnainternet.fi (dfj-tpyj40kccf8214dxy-3.rev.dnainternet.fi [IPv6:2001:14ba:21ff:600:f8f2:422:72d5:c0e6]) by galahad.ideasonboard.com (Postfix) with ESMTPSA id 45B1520FD1; Tue, 17 Jan 2017 09:28:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1484641718; bh=UUHd+ExwKzS1+8I7ZpyV15O5y9B268+xW8k8gh24aW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LGJLJUHlYNXB/YVi+19So0TARTmaQ+UBoUp6HYh3wHz5sjJ/MKk5NP/Ol5RJZK3+G 1qaV9H5KkwixFL7jc2AOyYyBppGnMb3gaseRjCE7Un+C+YNNYrZ7uXRUHw67c3xlBJ qXi6mLPOJpxRsGgbWn7H9ZZSOciwAlPGDPtoNgoo= From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org, Andy Yan , Archit Taneja , Fabio Estevam , Jose Abreu , Kieran Bingham , Nickey Yang , Russell King , Vladimir Zapolskiy Subject: [PATCH v3 18/20] drm: bridge: dw-hdmi: Fix the name of the PHY reset macros Date: Tue, 17 Jan 2017 10:29:08 +0200 Message-Id: <20170117082910.27023-19-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170117082910.27023-1-laurent.pinchart+renesas@ideasonboard.com> References: <20170117082910.27023-1-laurent.pinchart+renesas@ideasonboard.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The PHY reset signal is controlled by bit PHYRSTZ in the MC_PHYRSTZ register. The signal is active low on Gen1 PHYs and active high on Gen2 PHYs. The driver toggles the signal high then low, which is correct for all currently supported platforms, but the register values macros are incorrectly named. Replace them with a single macro named after the bit, and add a comment to the source code to explain the behaviour. The driver's behaviour isn't changed by this rename, the code will still need to be fixed to support Gen1 PHYs. Signed-off-by: Laurent Pinchart Reviewed-by: Jose Abreu --- drivers/gpu/drm/bridge/dw-hdmi.c | 6 +++--- drivers/gpu/drm/bridge/dw-hdmi.h | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/dw-hdmi.c b/drivers/gpu/drm/bridge/dw-hdmi.c index 6e605fd910ef..93e8816f1f78 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/dw-hdmi.c @@ -986,9 +986,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, int cscon) /* gen2 pddq */ dw_hdmi_phy_gen2_pddq(hdmi, 1); - /* PHY reset */ - hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); - hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); + /* PHY reset. The reset signal is active high on Gen2 PHYs. */ + hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); + hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); diff --git a/drivers/gpu/drm/bridge/dw-hdmi.h b/drivers/gpu/drm/bridge/dw-hdmi.h index f3c149c88d71..325b0b8ae639 100644 --- a/drivers/gpu/drm/bridge/dw-hdmi.h +++ b/drivers/gpu/drm/bridge/dw-hdmi.h @@ -989,8 +989,7 @@ enum { HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, /* MC_PHYRSTZ field values */ - HDMI_MC_PHYRSTZ_ASSERT = 0x0, - HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + HDMI_MC_PHYRSTZ_PHYRSTZ = 0x01, /* MC_HEACPHY_RST field values */ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,