| Message ID | 20170301225455.22818-4-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
Hello! On 3/2/2017 1:54 AM, Chris Brandt wrote: > Add watchdog timer support for RZ/A1. > For the RZ/A1, the only way to do a reset is to overflow the WDT, so this > is useful even if you don't need the watchdog functionality. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- > v3: > * added Reviewed-by > v2: > * changed "renesas,r7s72100-reset" to "renesas,r7s72100-wdt" > * changed "renesas,wdt-reset" to "renesas,rza-wdt" > * added interupt property (even though it is not used) > * added clocks property > --- > arch/arm/boot/dts/r7s72100.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi > index ed62e19..6ecee72 100644 > --- a/arch/arm/boot/dts/r7s72100.dtsi > +++ b/arch/arm/boot/dts/r7s72100.dtsi > @@ -382,6 +382,13 @@ > cache-level = <2>; > }; > > + wdt: timer@fcfe0000 { Why not watchdog@...? That name is standardized in ePAPR... > + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; > + reg = <0xfcfe0000 0x6>; > + interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>; > + clocks = <&p0_clk>; > + }; > + [...] MBR, Sergei
Hello Sergei, On Thursday, March 02, 2017, Sergei Shtylyov wrote: > > diff --git a/arch/arm/boot/dts/r7s72100.dtsi > > b/arch/arm/boot/dts/r7s72100.dtsi index ed62e19..6ecee72 100644 > > --- a/arch/arm/boot/dts/r7s72100.dtsi > > +++ b/arch/arm/boot/dts/r7s72100.dtsi > > @@ -382,6 +382,13 @@ > > cache-level = <2>; > > }; > > > > + wdt: timer@fcfe0000 { > > Why not watchdog@...? That name is standardized in ePAPR... > You are right. I'll change that. Thank you! Chris
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index ed62e19..6ecee72 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -382,6 +382,13 @@ cache-level = <2>; }; + wdt: timer@fcfe0000 { + compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt"; + reg = <0xfcfe0000 0x6>; + interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>; + clocks = <&p0_clk>; + }; + i2c0: i2c@fcfee000 { #address-cells = <1>; #size-cells = <0>;