From patchwork Fri Apr 28 18:52:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9705249 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40C8D602BF for ; Fri, 28 Apr 2017 18:52:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2CD1A28696 for ; Fri, 28 Apr 2017 18:52:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 203462869B; Fri, 28 Apr 2017 18:52:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, UPPERCASE_50_75 autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 32F6B28696 for ; Fri, 28 Apr 2017 18:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1035482AbdD1Swx (ORCPT ); Fri, 28 Apr 2017 14:52:53 -0400 Received: from mail-lf0-f43.google.com ([209.85.215.43]:33226 "EHLO mail-lf0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030652AbdD1Swv (ORCPT ); Fri, 28 Apr 2017 14:52:51 -0400 Received: by mail-lf0-f43.google.com with SMTP id 88so38623517lfr.0 for ; Fri, 28 Apr 2017 11:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:message-id:user-agent:date:to:cc:subject:mime-version :content-disposition; bh=NlhsBYZgjNChWGfuo0uprOpmZ5egoB2DhjmvkZJef7U=; b=y8H6tJroELuEMocs6d6cl4R08ldzS8VM6IKg6ukHh6pmwCEODFnXM0JSsOVt9ZReyV jqjIOTg5Z14FS/UOn9hPa9mVyN8cHzxElldjzQzASr/eLSpxcuSvlvvc3yXJ3XQyc45V V6uy8a6db2TP6F0fVNktVybHj9ZC2asS1TmnSSbik6vDZQ2vdaVA5SGwWsVVWP7XIEIC 4JEpjbX8VMJoShb7p+CB4BEJUrvP85m5pU1JcLtaT2Szq3K30p3/iko7Zi88YJdK6fAs jCiF7dA9fBEJPLggO10wbtTjS/8Qvfr5bM4M3mBvDuDYfsMa4Xxnoco65L4DTBS64Cp2 u/AA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:message-id:user-agent:date:to:cc:subject :mime-version:content-disposition; bh=NlhsBYZgjNChWGfuo0uprOpmZ5egoB2DhjmvkZJef7U=; b=ni56zzXO/rzizlej3fldu8JrFAAy95ZJFc+0tOobPlg6MawpE6kDNZYEVOSmvHqC0F e47GtR0UW8H9Zt44iHRRsbf7ylJ7PB3rB8lARjutDlQaSx3/Jmx4ZR5dDWPmAAkZbnig 8Co9KW5vMJaX6g1evOPNrQ+/5vT7Ni5OXuSLGJ3IY+xDv/USXHEtyfnMna5DHN+1NkMN zXB9VZeIcIad/dDMthzAe9TnCUSmbQx48+Zj/tD+JM2QF9a52fxWl1cVFxW9IWir6sNH gNVdDY1ejC6aGhqTzD201aLRhYJySAUBdt6CiMfDUDZYuH4iv3Szq1JJs2HTn7XiA/pL MCGw== X-Gm-Message-State: AN3rC/7qkucOE9tcAMvsYNd9/l2o7a7HqaGJi28cjJLWRkbWcuXWGKB6 AP4/m2f2wIqb9Q== X-Received: by 10.46.87.73 with SMTP id r9mr4867826ljd.31.1493405569401; Fri, 28 Apr 2017 11:52:49 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.86.14]) by smtp.gmail.com with ESMTPSA id k141sm1195972lfg.12.2017.04.28.11.52.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Apr 2017 11:52:48 -0700 (PDT) From: Sergei Shtylyov X-Google-Original-From: "Sergei Shtylyov" Received: by wasted.cogentembedded.com (sSMTP sendmail emulation); Fri, 28 Apr 2017 21:52:45 +0300 Message-Id: <20170428185245.428747882@cogentembedded.com> User-Agent: quilt/0.64 Date: Fri, 28 Apr 2017 21:52:35 +0300 To: Rob Herring , Mark Rutland , Laurent Pinchart , Geert Uytterhoeven , Linus Walleij , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Sergei Shtylyov Subject: [PATCH v3] pinctrl: sh-pfc: r8a7794: add R8A7745 support MIME-Version: 1.0 Content-Disposition: inline; filename=pinctrl-sh-pfc-r8a7794-add-R8A7745-support-v3.patch Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Renesas RZ/G1E (R8A7745) is pin compatible with R-Car E2 (R8A7794), however it doesn't have several automotive specific peripherals. Annotate all the items that only exist on the R-Car SoCs... Signed-off-by: Sergei Shtylyov Acked-by: Rob Herring --- This patch is against the 'devel' branch of Linus Walleij's 'linux-pinctrl.git' repo plus 3 R8A7794 PFC driver fixes/cleanups posted today and the R8A7743 PFC support patch posted last week... Changes in version 3: - resolved rejects atop of the new R8A7794 driver patches renaming the IIC0/1 signals and removing reserved groups/signals; - undid splitting of 'pinmux_{groups|functions}' arrays into the common and R8A7794 specfic parts, updated the patch description accordingly; - kill double spaces in the patch description. Changes in version 2: - fixed indentation to use tabs instead of spaces; - updated the PFC bindings. Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 drivers/pinctrl/sh-pfc/Kconfig | 5 drivers/pinctrl/sh-pfc/Makefile | 1 drivers/pinctrl/sh-pfc/core.c | 6 drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 640 +++++----- drivers/pinctrl/sh-pfc/sh_pfc.h | 1 6 files changed, 369 insertions(+), 285 deletions(-) Index: linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt =================================================================== --- linux-pinctrl.orig/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ linux-pinctrl/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -14,6 +14,7 @@ Required Properties: - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. + - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Kconfig +++ linux-pinctrl/drivers/pinctrl/sh-pfc/Kconfig @@ -39,6 +39,11 @@ config PINCTRL_PFC_R8A7743 depends on ARCH_R8A7743 select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A7745 + def_bool y + depends on ARCH_R8A7745 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7778 def_bool y depends on ARCH_R8A7778 Index: linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/Makefile +++ linux-pinctrl/drivers/pinctrl/sh-pfc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-e obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o Index: linux-pinctrl/drivers/pinctrl/sh-pfc/core.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/core.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/core.c @@ -491,6 +491,12 @@ static const struct of_device_id sh_pfc_ .data = &r8a7743_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7745 + { + .compatible = "renesas,pfc-r8a7745", + .data = &r8a7745_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { .compatible = "renesas,pfc-r8a7778", Index: linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ linux-pinctrl/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -1,9 +1,9 @@ /* - * r8a7794 processor support - PFC hardware block. + * r8a7794/r8a7745 processor support - PFC hardware block. * * Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. - * Copyright (C) 2015-2016 Cogent Embedded, Inc., + * Copyright (C) 2015-2017 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 @@ -132,8 +132,8 @@ enum { FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, - FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C, - FN_TPUTO2_B, + FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN /* R8A7794 only */, + FN_CAN_CLK_C, FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, @@ -149,13 +149,16 @@ enum { FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, - FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3, - FN_SCIFB2_TXD, - FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK, + FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B /* R8A7794 only */, + FN_TPUTO3, FN_SCIFB2_TXD, + FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, + FN_TS_SCK_B /* R8A7794 only */, FN_BPFCLK /* R8A7794 only */, FN_SCIFB2_SCK, - FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK, + FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, + FN_TS_SDEN_B /* R8A7794 only */, FN_FMCLK /* R8A7794 only */, FN_SCIFB2_CTS_N, - FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN, + FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, + FN_TS_SPSYNC_B /* R8A7794 only */, FN_FMIN /* R8A7794 only */, FN_SCIFB2_RTS_N, FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_RD_N, FN_ATACS11_N, @@ -163,42 +166,48 @@ enum { /* IPSR4 */ FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, - FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, - FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, - FN_DU0_DR2, FN_LCDOUT18, - FN_DU0_DR3, FN_LCDOUT19, - FN_DU0_DR4, FN_LCDOUT20, - FN_DU0_DR5, FN_LCDOUT21, - FN_DU0_DR6, FN_LCDOUT22, - FN_DU0_DR7, FN_LCDOUT23, - FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, - FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, - FN_DU0_DG2, FN_LCDOUT10, - FN_DU0_DG3, FN_LCDOUT11, - FN_DU0_DG4, FN_LCDOUT12, + FN_DU0_DR0, FN_LCDOUT16 /* R8A7794 only */, FN_SCIF5_RXD_C, + FN_I2C2_SCL_D, + FN_DU0_DR1, FN_LCDOUT17 /* R8A7794 only */, FN_SCIF5_TXD_C, + FN_I2C2_SDA_D, + FN_DU0_DR2, FN_LCDOUT18 /* R8A7794 only */, + FN_DU0_DR3, FN_LCDOUT19 /* R8A7794 only */, + FN_DU0_DR4, FN_LCDOUT20 /* R8A7794 only */, + FN_DU0_DR5, FN_LCDOUT21 /* R8A7794 only */, + FN_DU0_DR6, FN_LCDOUT22 /* R8A7794 only */, + FN_DU0_DR7, FN_LCDOUT23 /* R8A7794 only */, + FN_DU0_DG0, FN_LCDOUT8 /* R8A7794 only */, FN_SCIFA0_RXD_C, + FN_I2C3_SCL_D, + FN_DU0_DG1, FN_LCDOUT9 /* R8A7794 only */, FN_SCIFA0_TXD_C, + FN_I2C3_SDA_D, + FN_DU0_DG2, FN_LCDOUT10 /* R8A7794 only */, + FN_DU0_DG3, FN_LCDOUT11 /* R8A7794 only */, + FN_DU0_DG4, FN_LCDOUT12 /* R8A7794 only */, /* IPSR5 */ - FN_DU0_DG5, FN_LCDOUT13, - FN_DU0_DG6, FN_LCDOUT14, - FN_DU0_DG7, FN_LCDOUT15, - FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, - FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C, - FN_DU0_DB2, FN_LCDOUT2, - FN_DU0_DB3, FN_LCDOUT3, - FN_DU0_DB4, FN_LCDOUT4, - FN_DU0_DB5, FN_LCDOUT5, - FN_DU0_DB6, FN_LCDOUT6, - FN_DU0_DB7, FN_LCDOUT7, - FN_DU0_DOTCLKIN, FN_QSTVA_QVS, - FN_DU0_DOTCLKOUT0, FN_QCLK, - FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, - FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, + FN_DU0_DG5, FN_LCDOUT13 /* R8A7794 only */, + FN_DU0_DG6, FN_LCDOUT14 /* R8A7794 only */, + FN_DU0_DG7, FN_LCDOUT15 /* R8A7794 only */, + FN_DU0_DB0, FN_LCDOUT0 /* R8A7794 only */, FN_SCIFA4_RXD_C, + FN_I2C4_SCL_D, FN_CAN0_RX_C, + FN_DU0_DB1, FN_LCDOUT1 /* R8A7794 only */, FN_SCIFA4_TXD_C, + FN_I2C4_SDA_D, FN_CAN0_TX_C, + FN_DU0_DB2, FN_LCDOUT2 /* R8A7794 only */, + FN_DU0_DB3, FN_LCDOUT3 /* R8A7794 only */, + FN_DU0_DB4, FN_LCDOUT4 /* R8A7794 only */, + FN_DU0_DB5, FN_LCDOUT5 /* R8A7794 only */, + FN_DU0_DB6, FN_LCDOUT6 /* R8A7794 only */, + FN_DU0_DB7, FN_LCDOUT7 /* R8A7794 only */, + FN_DU0_DOTCLKIN, FN_QSTVA_QVS /* R8A7794 only */, + FN_DU0_DOTCLKOUT0, FN_QCLK /* R8A7794 only */, + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE /* R8A7794 only */, + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS /* R8A7794 only */, /* IPSR6 */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, - FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, - FN_DU0_DISP, FN_QPOLA, - FN_DU0_CDE, FN_QPOLB, + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE /* R8A7794 only */, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE /* R8A7794 only */, + FN_DU0_DISP, FN_QPOLA /* R8A7794 only */, + FN_DU0_CDE, FN_QPOLB /* R8A7794 only */, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, @@ -208,25 +217,28 @@ enum { FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, - FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, - FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, - FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, + FN_IETX_C /* R8A7794 only */, FN_AVB_RXD7, + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, + FN_IECLK_C /* R8A7794 only */, FN_AVB_RX_ER, + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, + FN_IERX_C /* R8A7794 only */, FN_AVB_COL, FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, - FN_ADIDATA, + FN_ADIDATA /* R8A7794 only */, /* IPSR7 */ FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0, - FN_ADICS_SAMP, + FN_ADICS_SAMP /* R8A7794 only */, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1, - FN_ADICLK, + FN_ADICLK /* R8A7794 only */, FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, - FN_ADICHS0, + FN_ADICHS0 /* R8A7794 only */, FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, - FN_ADICHS1, + FN_ADICHS1 /* R8A7794 only */, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4, - FN_ADICHS2, + FN_ADICHS2 /* R8A7794 only */, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, @@ -253,26 +265,32 @@ enum { FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, - FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D, - FN_TPUTO1_B, - FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D, - FN_BPFCLK_C, - FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D, - FN_FMCLK_C, + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, + FN_TS_SDATA_D /* R8A7794 only */, FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, + FN_TS_SCK_D /* R8A7794 only */, FN_BPFCLK_C /* R8A7794 only */, + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, + FN_TS_SDEN_D /* R8A7794 only */, FN_FMCLK_C /* R8A7794 only */, /* IPSR9 */ - FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D, - FN_FMIN_C, - FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C, - FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B, - FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B, - FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B, + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, + FN_TS_SPSYNC_D /* R8A7794 only */, FN_FMIN_C /* R8A7794 only */, + FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA /* R8A7794 only */, FN_DU1_DR4, + FN_TPUTO1_C, + FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK /* R8A7794 only */, FN_DU1_DR5, + FN_BPFCLK_B /* R8A7794 only */, + FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN /* R8A7794 only */, FN_DU1_DR6, + FN_FMCLK_B /* R8A7794 only */, + FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC /* R8A7794 only */, + FN_DU1_DR7, FN_FMIN_B /* R8A7794 only */, FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, - FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, - FN_SPEEDIN_B, - FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B, - FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, + FN_HSCIF1_HSCK, FN_PWM2, FN_IETX /* R8A7794 only */, FN_DU1_DG2, + FN_REMOCON_B /* R8A7794 only */, FN_SPEEDIN_B /* R8A7794 only */, + FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK /* R8A7794 only */, + FN_DU1_DG3, FN_SSI_SCK1_B, + FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX /* R8A7794 only */, + FN_DU1_DG4, FN_SSI_WS1_B, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B, /* IPSR10 */ @@ -281,11 +299,12 @@ enum { FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, - FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B, - FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, - FN_SSI_SCK4_B, - FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, - FN_SSI_WS4_B, + FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D /* R8A7794 only */, FN_DU1_DB3, + FN_SSI_SDATA9_B, + FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D /* R8A7794 only */, FN_DU1_DB4, + FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, + FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D /* R8A7794 only */, FN_DU1_DB5, + FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, @@ -301,21 +320,28 @@ enum { FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, - FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, - FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, - FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, + FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, + FN_ADIDATA_B /* R8A7794 only */, + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, + FN_ADICS_SAMP_B /* R8A7794 only */, + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, + FN_ADICLK_B /* R8A7794 only */, /* IPSR12 */ - FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - FN_DREQ1_N_B, - FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, - FN_CAN1_RX_C, FN_DACK1_B, - FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, - FN_CAN1_TX_C, FN_DREQ2_N, - FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, - FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, - FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON, - FN_DACK2, FN_ETH_MDIO_B, + FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, + FN_ADICHS0_B /* R8A7794 only */, FN_DREQ1_N_B, + FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, + FN_ADICHS1_B /* R8A7794 only */, FN_CAN1_RX_C, FN_DACK1_B, + FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, + FN_ADICHS2_B /* R8A7794 only */, FN_CAN1_TX_C, FN_DREQ2_N, + FN_SSI_SCK4, FN_MLB_CLK /* R8A7794 only */, + FN_IETX_B /* R8A7794 only */, + FN_SSI_WS4, FN_MLB_SIG /* R8A7794 only */, + FN_IECLK_B /* R8A7794 only */, + FN_SSI_SDATA4, FN_MLB_DAT /* R8A7794 only */, + FN_IERX_B /* R8A7794 only */, + FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, + FN_REMOCON /* R8A7794 only */, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, @@ -336,19 +362,20 @@ enum { FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, - FN_TS_SDATA_C, FN_ETH_TXD0_B, + FN_TS_SDATA_C /* R8A7794 only */, FN_ETH_TXD0_B, FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, - FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B, + FN_TS_SCK_C /* R8A7794 only */, FN_BPFCLK_E /* R8A7794 only */, + FN_ETH_MDC_B, FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, - FN_TS_SDEN_C, FN_FMCLK_E, + FN_TS_SDEN_C /* R8A7794 only */, FN_FMCLK_E /* R8A7794 only */, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, - FN_TS_SPSYNC_C, FN_FMIN_E, + FN_TS_SPSYNC_C /* R8A7794 only */, FN_FMIN_E /* R8A7794 only */, /* MOD_SEL */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, - FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, - FN_SEL_DARC_4, + /* R8A7794 only */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, + /* R8A7794 only */ FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, @@ -363,18 +390,20 @@ enum { FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, /* MOD_SEL2 */ - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + /* R8A7794 only */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, - FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, + /* R8A7794 only */ FN_SEL_RCN_0, FN_SEL_RCN_1, + /* R8A7794 only */ FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_TMU_0, FN_SEL_TMU_1, - FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + /* R8A7794 only */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, + /* R8A7794 only */ FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, @@ -443,8 +472,8 @@ enum { A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK, - A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, - CAN_CLK_C_MARK, TPUTO2_B_MARK, + A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, + SPEEDIN_MARK /* R8A7794 only */, CAN_CLK_C_MARK, TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK, A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, @@ -460,57 +489,65 @@ enum { CS1_N_A26_MARK, VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, - EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, - TPUTO3_MARK, SCIFB2_TXD_MARK, - EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, - BPFCLK_MARK, SCIFB2_SCK_MARK, - EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, - FMCLK_MARK, SCIFB2_CTS_N_MARK, - EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, - FMIN_MARK, SCIFB2_RTS_N_MARK, + EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, + TS_SDATA_B_MARK /* R8A7794 only */, TPUTO3_MARK, SCIFB2_TXD_MARK, + EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, + TS_SCK_B_MARK /* R8A7794 only */, BPFCLK_MARK /* R8A7794 only */, + SCIFB2_SCK_MARK, + EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, + TS_SDEN_B_MARK /* R8A7794 only */, FMCLK_MARK /* R8A7794 only */, + SCIFB2_CTS_N_MARK, + EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, + TS_SPSYNC_B_MARK /* R8A7794 only */, FMIN_MARK /* R8A7794 only */, + SCIFB2_RTS_N_MARK, BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, RD_N_MARK, ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, /* IPSR4 */ EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, - DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, - DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK, - DU0_DR2_MARK, LCDOUT18_MARK, - DU0_DR3_MARK, LCDOUT19_MARK, - DU0_DR4_MARK, LCDOUT20_MARK, - DU0_DR5_MARK, LCDOUT21_MARK, - DU0_DR6_MARK, LCDOUT22_MARK, - DU0_DR7_MARK, LCDOUT23_MARK, - DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, - DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK, - DU0_DG2_MARK, LCDOUT10_MARK, - DU0_DG3_MARK, LCDOUT11_MARK, - DU0_DG4_MARK, LCDOUT12_MARK, + DU0_DR0_MARK, LCDOUT16_MARK /* R8A7794 only */, SCIF5_RXD_C_MARK, + I2C2_SCL_D_MARK, + DU0_DR1_MARK, LCDOUT17_MARK /* R8A7794 only */, SCIF5_TXD_C_MARK, + I2C2_SDA_D_MARK, + DU0_DR2_MARK, LCDOUT18_MARK /* R8A7794 only */, + DU0_DR3_MARK, LCDOUT19_MARK /* R8A7794 only */, + DU0_DR4_MARK, LCDOUT20_MARK /* R8A7794 only */, + DU0_DR5_MARK, LCDOUT21_MARK /* R8A7794 only */, + DU0_DR6_MARK, LCDOUT22_MARK /* R8A7794 only */, + DU0_DR7_MARK, LCDOUT23_MARK /* R8A7794 only */, + DU0_DG0_MARK, LCDOUT8_MARK /* R8A7794 only */, SCIFA0_RXD_C_MARK, + I2C3_SCL_D_MARK, + DU0_DG1_MARK, LCDOUT9_MARK /* R8A7794 only */, SCIFA0_TXD_C_MARK, + I2C3_SDA_D_MARK, + DU0_DG2_MARK, LCDOUT10_MARK /* R8A7794 only */, + DU0_DG3_MARK, LCDOUT11_MARK /* R8A7794 only */, + DU0_DG4_MARK, LCDOUT12_MARK /* R8A7794 only */, /* IPSR5 */ - DU0_DG5_MARK, LCDOUT13_MARK, - DU0_DG6_MARK, LCDOUT14_MARK, - DU0_DG7_MARK, LCDOUT15_MARK, - DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK, - CAN0_RX_C_MARK, - DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, - CAN0_TX_C_MARK, - DU0_DB2_MARK, LCDOUT2_MARK, - DU0_DB3_MARK, LCDOUT3_MARK, - DU0_DB4_MARK, LCDOUT4_MARK, - DU0_DB5_MARK, LCDOUT5_MARK, - DU0_DB6_MARK, LCDOUT6_MARK, - DU0_DB7_MARK, LCDOUT7_MARK, - DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, - DU0_DOTCLKOUT0_MARK, QCLK_MARK, - DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, - DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, + DU0_DG5_MARK, LCDOUT13_MARK /* R8A7794 only */, + DU0_DG6_MARK, LCDOUT14_MARK /* R8A7794 only */, + DU0_DG7_MARK, LCDOUT15_MARK /* R8A7794 only */, + DU0_DB0_MARK, LCDOUT0_MARK /* R8A7794 only */, SCIFA4_RXD_C_MARK, + I2C4_SCL_D_MARK, CAN0_RX_C_MARK, + DU0_DB1_MARK, LCDOUT1_MARK /* R8A7794 only */, SCIFA4_TXD_C_MARK, + I2C4_SDA_D_MARK, CAN0_TX_C_MARK, + DU0_DB2_MARK, LCDOUT2_MARK /* R8A7794 only */, + DU0_DB3_MARK, LCDOUT3_MARK /* R8A7794 only */, + DU0_DB4_MARK, LCDOUT4_MARK /* R8A7794 only */, + DU0_DB5_MARK, LCDOUT5_MARK /* R8A7794 only */, + DU0_DB6_MARK, LCDOUT6_MARK /* R8A7794 only */, + DU0_DB7_MARK, LCDOUT7_MARK /* R8A7794 only */, + DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK /* R8A7794 only */, + DU0_DOTCLKOUT0_MARK, QCLK_MARK /* R8A7794 only */, + DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK /* R8A7794 only */, + DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK /* R8A7794 only */, /* IPSR6 */ - DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, - DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, - DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK /* R8A7794 only */, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK /* R8A7794 only */, + DU0_DISP_MARK, QPOLA_MARK /* R8A7794 only */, + DU0_CDE_MARK, QPOLB_MARK /* R8A7794 only */, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, @@ -519,28 +556,28 @@ enum { VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, - VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, - AVB_RXD7_MARK, - VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, - AVB_RX_ER_MARK, - VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK, - AVB_COL_MARK, + VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, + IETX_C_MARK /* R8A7794 only */, AVB_RXD7_MARK, + VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, + IECLK_C_MARK /* R8A7794 only */, AVB_RX_ER_MARK, + VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, + IERX_C_MARK /* R8A7794 only */, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, - AVB_TX_CLK_MARK, ADIDATA_MARK, + AVB_TX_CLK_MARK, ADIDATA_MARK /* R8A7794 only */, /* IPSR7 */ ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK, - AVB_TXD0_MARK, ADICS_SAMP_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK /* R8A7794 only */, ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, - AVB_TXD1_MARK, ADICLK_MARK, + AVB_TXD1_MARK, ADICLK_MARK /* R8A7794 only */, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK, - AVB_TXD2_MARK, ADICHS0_MARK, + AVB_TXD2_MARK, ADICHS0_MARK /* R8A7794 only */, ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, - AVB_TXD3_MARK, ADICHS1_MARK, + AVB_TXD3_MARK, ADICHS1_MARK /* R8A7794 only */, ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, - AVB_TXD4_MARK, ADICHS2_MARK, + AVB_TXD4_MARK, ADICHS2_MARK /* R8A7794 only */, ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK, @@ -568,31 +605,34 @@ enum { SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK, - TS_SDATA_D_MARK, TPUTO1_B_MARK, - I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK, - BPFCLK_C_MARK, + TS_SDATA_D_MARK /* R8A7794 only */, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, + TS_SCK_D_MARK /* R8A7794 only */, BPFCLK_C_MARK /* R8A7794 only */, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK, - TS_SDEN_D_MARK, FMCLK_C_MARK, + TS_SDEN_D_MARK /* R8A7794 only */, FMCLK_C_MARK /* R8A7794 only */, /* IPSR9 */ MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, - TS_SPSYNC_D_MARK, FMIN_C_MARK, - MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK, - MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK, - MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK, - FMCLK_B_MARK, - MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, - FMIN_B_MARK, + TS_SPSYNC_D_MARK /* R8A7794 only */, FMIN_C_MARK /* R8A7794 only */, + MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK /* R8A7794 only */, + DU1_DR4_MARK, TPUTO1_C_MARK, + MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK /* R8A7794 only */, + DU1_DR5_MARK, BPFCLK_B_MARK /* R8A7794 only */, + MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK /* R8A7794 only */, + DU1_DR6_MARK, FMCLK_B_MARK /* R8A7794 only */, + MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK /* R8A7794 only */, + DU1_DR7_MARK, FMIN_B_MARK /* R8A7794 only */, HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, - HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, - SPEEDIN_B_MARK, - HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK, - SSI_SCK1_B_MARK, - HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK, - SSI_WS1_B_MARK, + HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK /* R8A7794 only */, + DU1_DG2_MARK, REMOCON_B_MARK /* R8A7794 only */, + SPEEDIN_B_MARK /* R8A7794 only */, + HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK /* R8A7794 only */, + DU1_DG3_MARK, SSI_SCK1_B_MARK, + HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK /* R8A7794 only */, + DU1_DG4_MARK, SSI_WS1_B_MARK, SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, - CAN_TXCLK_MARK, + CAN_TXCLK_MARK /* R8A7794 only */, /* IPSR10 */ SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, @@ -600,12 +640,12 @@ enum { SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK, - SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK, - SSI_SDATA9_B_MARK, - SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK, - AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, - SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK, - AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, + SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK /* R8A7794 only */, + DU1_DB3_MARK, SSI_SDATA9_B_MARK, + SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK /* R8A7794 only */, + DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, + SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK /* R8A7794 only */, + DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, @@ -623,22 +663,28 @@ enum { SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, - SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, - SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK, - SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK, + SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, + ADIDATA_B_MARK /* R8A7794 only */, + SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, + ADICS_SAMP_B_MARK /* R8A7794 only */, + SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, + ADICLK_B_MARK /* R8A7794 only */, /* IPSR12 */ - SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, - DREQ1_N_B_MARK, - SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, - CAN1_RX_C_MARK, DACK1_B_MARK, - SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, - CAN1_TX_C_MARK, DREQ2_N_MARK, - SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, - SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, - SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, - SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, - DACK2_MARK, ETH_MDIO_B_MARK, + SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, + ADICHS0_B_MARK /* R8A7794 only */, DREQ1_N_B_MARK, + SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, + ADICHS1_B_MARK /* R8A7794 only */, CAN1_RX_C_MARK, DACK1_B_MARK, + SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, + ADICHS2_B_MARK /* R8A7794 only */, CAN1_TX_C_MARK, DREQ2_N_MARK, + SSI_SCK4_MARK, MLB_CLK_MARK /* R8A7794 only */, + IETX_B_MARK /* R8A7794 only */, + SSI_WS4_MARK, MLB_SIG_MARK /* R8A7794 only */, + IECLK_B_MARK /* R8A7794 only */, + SSI_SDATA4_MARK, MLB_DAT_MARK /* R8A7794 only */, + IERX_B_MARK /* R8A7794 only */, + SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, + REMOCON_MARK /* R8A7794 only */, DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK, @@ -660,13 +706,14 @@ enum { SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK, - TS_SDATA_C_MARK, ETH_TXD0_B_MARK, + TS_SDATA_C_MARK /* R8A7794 only */, ETH_TXD0_B_MARK, AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, - TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, + TS_SCK_C_MARK /* R8A7794 only */, BPFCLK_E_MARK /* R8A7794 only */, + ETH_MDC_B_MARK, AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, - TS_SDEN_C_MARK, FMCLK_E_MARK, + TS_SDEN_C_MARK /* R8A7794 only */, FMCLK_E_MARK /* R8A7794 only */, AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, - TS_SPSYNC_C_MARK, FMIN_E_MARK, + TS_SPSYNC_C_MARK /* R8A7794 only */, FMIN_E_MARK /* R8A7794 only */, PINMUX_MARK_END, }; @@ -831,7 +878,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP2_20_18, A16), PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), - PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), + PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B), PINMUX_IPSR_GPSR(IP2_23_21, A17), @@ -877,26 +924,26 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N), PINMUX_IPSR_GPSR(IP3_17_15, PWM0), PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), + PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3), PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD), PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N), PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), - PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK), PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N), PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), - PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N), PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N), PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), - PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), + PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), /* R8A7794 */ + PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N), PINMUX_IPSR_GPSR(IP3_29_27, BS_N), PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), @@ -913,87 +960,87 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0), - PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), + PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1), - PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), + PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2), - PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), + PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3), - PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), + PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4), - PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), + PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5), - PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), + PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6), - PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), + PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7), - PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), + PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0), - PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), + PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1), - PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), + PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2), - PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), + PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3), - PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), + PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4), - PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), + PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), /* R8A7794 only */ /* IPSR5 */ PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5), - PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), + PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6), - PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), + PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7), - PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), + PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0), - PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), + PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1), - PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), + PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2), - PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), + PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3), - PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), + PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4), - PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), + PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5), - PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), + PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6), - PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), + PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7), - PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), + PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN), - PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), + PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0), - PINMUX_IPSR_GPSR(IP5_27_26, QCLK), + PINMUX_IPSR_GPSR(IP5_27_26, QCLK), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1), - PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), + PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), - PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), + PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), /* R8A7794 only */ /* IPSR6 */ PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), - PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), + PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), - PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), + PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP), - PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), + PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE), - PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), + PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_8, VI0_CLK), PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK), PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0), @@ -1015,17 +1062,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB), PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0), PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7), PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD), PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0), PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), - PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER), PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N), PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), - PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), + PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL), PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N), PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), @@ -1037,7 +1084,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3), PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK), - PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), /* R8A7794 only */ /* IPSR7 */ PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), @@ -1045,7 +1092,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3), PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0), - PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2), PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), @@ -1057,19 +1104,19 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2), - PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4), PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3), - PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5), PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4), - PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), + PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6), PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), @@ -1153,48 +1200,48 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B), PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0), - PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), + PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B), PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP8_28_26, IRQ5), PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1), - PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD), PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2), - PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), /* R8A7794 only */ /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD), PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3), - PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), - PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), + PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK), PINMUX_IPSR_GPSR(IP9_5_3, IRQ0), - PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4), PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C), PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP9_8_6, PWM1), - PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5), - PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), - PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6), - PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), - PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), + PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7), - PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), + PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), PINMUX_IPSR_GPSR(IP9_16_15, PWM6), @@ -1205,18 +1252,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1), PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK), PINMUX_IPSR_GPSR(IP9_21_19, PWM2), - PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2), - PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), - PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), + PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), - PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3), PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), - PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), + PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4), PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), @@ -1248,18 +1295,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_GPSR(IP10_17_15, IRQ2), - PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3), PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), - PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4), PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), - PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), + PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5), PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), @@ -1312,48 +1359,48 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129), PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129), PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), - PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), /* R8A7794 */ PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0), PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B), - PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), /* R8A7794 only */ /* IPSR12 */ PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34), PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), - PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34), PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2), PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1), PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3), PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2), - PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), + PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2), PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N), PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), - PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), - PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), + PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), - PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), - PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), + PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), - PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), - PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), + PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B), PINMUX_IPSR_GPSR(IP12_17_15, IRQ9), - PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), + PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0), /* R8A7794 only */ PINMUX_IPSR_GPSR(IP12_17_15, DACK2), PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), @@ -1414,27 +1461,27 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1), PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB), - PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), + PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), /* R8A7794 */ PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD), - PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1), PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N), - PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), /* R8A7794 only */ + PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), /* R8A7794 only */ PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N), - PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), + PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), /* R8A7794 */ + PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), /* R8A7794 only */ }; static const struct sh_pfc_pin pinmux_pins[] = { @@ -4931,7 +4978,7 @@ static const struct pinmux_cfg_reg pinmu 0, 0, /* SEL_CAN [2] */ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, - /* SEL_DARC [3] */ + /* SEL_DARC [3] (R8A7794 only) */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, 0, 0, 0, /* RESERVED [4] */ @@ -4963,7 +5010,7 @@ static const struct pinmux_cfg_reg pinmu { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 2, 1, 1, 2) { - /* SEL_IEB [2] */ + /* SEL_IEB [2] (R8A7794 only) */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_IIC0 [2] */ FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, @@ -4975,9 +5022,9 @@ static const struct pinmux_cfg_reg pinmu FN_SEL_MSI2_0, FN_SEL_MSI2_1, /* SEL_RAD [1] */ FN_SEL_RAD_0, FN_SEL_RAD_1, - /* SEL_RCN [1] */ + /* SEL_RCN [1] (R8A7794 only) */ FN_SEL_RCN_0, FN_SEL_RCN_1, - /* SEL_RSP [1] */ + /* SEL_RSP [1] (R8A7794 only) */ FN_SEL_RSP_0, FN_SEL_RSP_1, /* SEL_SCIFA0 [2] */ FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, @@ -4998,7 +5045,7 @@ static const struct pinmux_cfg_reg pinmu 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU_0, FN_SEL_TMU_1, - /* SEL_TSIF0 [2] */ + /* SEL_TSIF0 [2] (R8A7794 only) */ FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, /* SEL_CAN0 [2] */ FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, @@ -5094,6 +5141,28 @@ static const struct sh_pfc_soc_operation .pin_to_pocctrl = r8a7794_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7745 +const struct sh_pfc_soc_info r8a7745_pinmux_info = { + .name = "r8a77450_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7794 const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", .ops = &r8a7794_pinmux_ops, @@ -5113,3 +5182,4 @@ const struct sh_pfc_soc_info r8a7794_pin .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif Index: linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h =================================================================== --- linux-pinctrl.orig/drivers/pinctrl/sh-pfc/sh_pfc.h +++ linux-pinctrl/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -260,6 +260,7 @@ extern const struct sh_pfc_soc_info emev extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; +extern const struct sh_pfc_soc_info r8a7745_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info;