From patchwork Sat Jul 1 20:04:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 9820963 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9AD43603F3 for ; Sat, 1 Jul 2017 20:05:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D095269E2 for ; Sat, 1 Jul 2017 20:05:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 814232844B; Sat, 1 Jul 2017 20:05:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF3EE2845D for ; Sat, 1 Jul 2017 20:05:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752038AbdGAUFk (ORCPT ); Sat, 1 Jul 2017 16:05:40 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:34004 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751996AbdGAUFj (ORCPT ); Sat, 1 Jul 2017 16:05:39 -0400 Received: by mail-wm0-f67.google.com with SMTP id p204so13610068wmg.1; Sat, 01 Jul 2017 13:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5/AuaJPn1J2yqQGK0p8fSVlvQL4T8nO9z7aAqqkYyJs=; b=it1o0BNSNYCYlg0JRAGud/U55X84QEHPI6duMbmaK82GpCggkuz8gKEOfOz6/WIGV0 xcopGhMUaTomAYzyyN/KdEXIXs+uGC+0NgHjBfhyop8kPPeFhl0UMdTULq7Gl5aUyM5i 1WBGStK+/miXc+whdOKgKOnLiZqA6oyHJgl6u/W7CpEAsciHA8ejDRaeUoxq71v/r6UW CYeYU1uiTCN8+cVybm+JA7EVs7oGNdwuyEHV7NjNn5i+FAG1E6Xy4BABNlHMDBiNsglF UisXZiyDfMraVXmJmTAfsG6lT+A0cq7MDGdGxY1dw+7agXorSOIIPBwZcxTg21fZvlLN FnyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5/AuaJPn1J2yqQGK0p8fSVlvQL4T8nO9z7aAqqkYyJs=; b=Qq9vOk4n1m7wb6Ni6lVmvQpMdGSdpZZgXp8ePwR72WK2XMaPm6ACJiGlonveZ6AT+C EA+LrL1GwnoZTzBCr7yQC37zTKXOCTI5x4UaGm5elm1oczFfgWYUeNcpidBoGuL8uE0+ xqg+c4y0E3j+XcLg2Qe6O/mDI8MdCVuboRKMuNhzYz4zWvZ2LMQVTmO6y5dYzr2qxnaS EXPuy4AMpVrYkyMGqmsFGkI9xPRa3gaaieGKz+duUQSJg75Lsyx0kNGqujfCyx7PeJQR Bu7jZ3B9Vzmz7lJkke9bRtktjaKUsLcNrG56QiedPB9ewqxQlrkvvu9HJpBY4Qbd1qM+ yWlg== X-Gm-Message-State: AKS2vOzOE0EDpR+uYnhE+NcyMiqs7mBge5DmDuR+Z7hFf90yLmeaNWyt VDx9vvH1zox15zkCGx8= X-Received: by 10.28.173.10 with SMTP id w10mr18562225wme.98.1498939537123; Sat, 01 Jul 2017 13:05:37 -0700 (PDT) Received: from kurokawa.lan (ip-86-49-107-50.net.upcbroadband.cz. [86.49.107.50]) by smtp.gmail.com with ESMTPSA id s30sm18150137wrc.13.2017.07.01.13.05.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 01 Jul 2017 13:05:36 -0700 (PDT) From: Marek Vasut X-Google-Original-From: Marek Vasut To: linux-clk@vger.kernel.org Cc: Marek Vasut , Stephen Boyd , Alexey Firago , Michael Turquette , Laurent Pinchart , linux-renesas-soc@vger.kernel.org Subject: [PATCH 6/8] clk: vc5: Add support for the input frequency doubler Date: Sat, 1 Jul 2017 22:04:56 +0200 Message-Id: <20170701200459.11505-6-marek.vasut+renesas@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170701200459.11505-1-marek.vasut+renesas@gmail.com> References: <20170701200459.11505-1-marek.vasut+renesas@gmail.com> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The VersaClock 6 has an input frequency doubler between the input clock mux and the predivider. Add new capability flag and support for this frequency doubler block into the driver. Signed-off-by: Marek Vasut Cc: Stephen Boyd Cc: Alexey Firago Cc: Michael Turquette Cc: Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org Tested-by: Laurent Pinchart on Salvator-XS with the display LVDS output. --- drivers/clk/clk-versaclock5.c | 78 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c index 453c9f721b78..d0406b62133a 100644 --- a/drivers/clk/clk-versaclock5.c +++ b/drivers/clk/clk-versaclock5.c @@ -57,6 +57,7 @@ #define VC5_PRIM_SRC_SHDN 0x10 #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) +#define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) #define VC5_PRIM_SRC_SHDN_SP BIT(1) #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) @@ -122,6 +123,8 @@ /* flags to describe chip features */ /* chip has built-in oscilator */ #define VC5_HAS_INTERNAL_XTAL BIT(0) +/* chip has PFD requency doubler */ +#define VC5_HAS_PFD_FREQ_DBL BIT(1) /* Supported IDT VC5 models. */ enum vc5_model { @@ -157,6 +160,7 @@ struct vc5_driver_data { struct clk *pin_clkin; unsigned char clk_mux_ins; struct clk_hw clk_mux; + struct clk_hw clk_mul; struct clk_hw clk_pfd; struct vc5_hw_data clk_pll; struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; @@ -167,6 +171,10 @@ static const char * const vc5_mux_names[] = { "mux" }; +static const char * const vc5_dbl_names[] = { + "dbl" +}; + static const char * const vc5_pfd_names[] = { "pfd" }; @@ -264,6 +272,54 @@ static const struct clk_ops vc5_mux_ops = { .get_parent = vc5_mux_get_parent, }; +static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct vc5_driver_data *vc5 = + container_of(hw, struct vc5_driver_data, clk_mul); + unsigned int premul; + + regmap_read(vc5->regmap, VC5_PRIM_SRC_SHDN, &premul); + if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) + parent_rate *= 2; + + return parent_rate; +} + +static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) + return rate; + else + return -EINVAL; +} + +static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct vc5_driver_data *vc5 = + container_of(hw, struct vc5_driver_data, clk_mul); + u32 mask; + + if ((parent_rate * 2) == rate) + mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; + else + mask = 0; + + regmap_update_bits(vc5->regmap, VC5_PRIM_SRC_SHDN, + VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, + mask); + + return 0; +} + +static const struct clk_ops vc5_dbl_ops = { + .recalc_rate = vc5_dbl_recalc_rate, + .round_rate = vc5_dbl_round_rate, + .set_rate = vc5_dbl_set_rate, +}; + static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -706,12 +762,32 @@ static int vc5_probe(struct i2c_client *client, goto err_clk; } + if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { + /* Register frequency doubler */ + memset(&init, 0, sizeof(init)); + init.name = vc5_dbl_names[0]; + init.ops = &vc5_dbl_ops; + init.flags = CLK_SET_RATE_PARENT; + init.parent_names = vc5_mux_names; + init.num_parents = 1; + vc5->clk_mul.init = &init; + ret = devm_clk_hw_register(&client->dev, &vc5->clk_mul); + if (ret) { + dev_err(&client->dev, "unable to register %s\n", + init.name); + goto err_clk; + } + } + /* Register PFD */ memset(&init, 0, sizeof(init)); init.name = vc5_pfd_names[0]; init.ops = &vc5_pfd_ops; init.flags = CLK_SET_RATE_PARENT; - init.parent_names = vc5_mux_names; + if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) + init.parent_names = vc5_dbl_names; + else + init.parent_names = vc5_mux_names; init.num_parents = 1; vc5->clk_pfd.init = &init; ret = devm_clk_hw_register(&client->dev, &vc5->clk_pfd);