From patchwork Sat Aug 5 20:52:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9883309 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 87CCC60392 for ; Sat, 5 Aug 2017 20:53:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7A5F52871C for ; Sat, 5 Aug 2017 20:53:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6EC78287AB; Sat, 5 Aug 2017 20:53:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 54D0A287B9 for ; Sat, 5 Aug 2017 20:53:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752081AbdHEUxN (ORCPT ); Sat, 5 Aug 2017 16:53:13 -0400 Received: from mail-wr0-f179.google.com ([209.85.128.179]:34048 "EHLO mail-wr0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751401AbdHEUxL (ORCPT ); Sat, 5 Aug 2017 16:53:11 -0400 Received: by mail-wr0-f179.google.com with SMTP id 12so27171124wrb.1 for ; Sat, 05 Aug 2017 13:53:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z7AJAzwrv8i6psYuqzfsm9AF3MgwmVusZzTSffJgUF0=; b=jtVDzefvCj/FRmySfR+47JZEidHY1m7dWug6s9xbBiQFlqXT7OgEm3S6eeybCsFj4c N+1kiaXvxJ559zxLrOmEpWvLFwjCRfhAZUqJE1YM5WCINrqv2z5erXVzywUauDuqu6Gd MG2QiQ+C9MUHdiCvaJo4nKgI9TBAHwBz4ehgs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z7AJAzwrv8i6psYuqzfsm9AF3MgwmVusZzTSffJgUF0=; b=gLSB9f/9LpGBb+7o2KiRsKJ0t0jjx3npJPoipHvR8xlNWfsqrkVj77huA9obCEHHZF B0IseaSj9KXB1QeMiEuV0TH3si2fKWaferaUM5HBF3mNQ2HybL586jyyszQEQlCYGZV8 i/tHFmyheKdvuHimp4v3/D1/2rp2aebGszFVrzOs5mQgyZPdrwRqJ5tUHMkVVagSiLWy Ch+8I/sSmmtffpjNAh4OLm4e1sn8zsMsXNyVHrYzn3cyFt8iyigYfRbOnxgz776AuBRw tJL/mZgtSJO4kSZQCMvkjJdqPLCLazPpiiPTzfKkwbmY1pw/235yxOcSBAr6MRzQ/PvB zWSA== X-Gm-Message-State: AIVw111bshZvnf7o3OQgJ+RI9VmQ7WkCcsvYpp9ofHwWVks0xUuoe2WO PvofetpO5ikLg0LP X-Received: by 10.223.163.16 with SMTP id c16mr5069436wrb.173.1501966390426; Sat, 05 Aug 2017 13:53:10 -0700 (PDT) Received: from localhost.localdomain ([160.77.147.147]) by smtp.gmail.com with ESMTPSA id v62sm2601775wmd.2.2017.08.05.13.53.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 05 Aug 2017 13:53:09 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux@armlinux.org.uk, linux-omap@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, krzk@kernel.org, jason@lakedaemon.net, arm@kernel.org, andrew@lunn.ch, gregory.clement@free-electrons.com, sebastian.hesselbarth@gmail.com, tony@atomide.com, baohua@kernel.org, horms@verge.net.au, magnus.damm@gmail.com, vireshk@kernel.org, shiraz.linux.kernel@gmail.com, patrice.chotard@st.com, nico@linaro.org, dave.martin@arm.com, marc.zyngier@arm.com Cc: Ard Biesheuvel Subject: [PATCH 01/15] ARM: assembler: introduce adr_l, ldr_l and str_l macros Date: Sat, 5 Aug 2017 21:52:08 +0100 Message-Id: <20170805205222.19868-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170805205222.19868-1-ard.biesheuvel@linaro.org> References: <20170805205222.19868-1-ard.biesheuvel@linaro.org> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Like arm64, ARM supports position independent code sequences that produce symbol references with a greater reach than the ordinary adr/ldr instructions. Currently, we use open coded instruction sequences involving literals and arithmetic operations. Instead, we can use movw/movt pairs on v7 CPUs, circumventing the D-cache entirely. For older CPUs, we can emit the literal into a subsection, allowing it to be emitted out of line while retaining the ability to perform arithmetic on label offsets. E.g., on pre-v7 CPUs, we can emit a PC-relative reference as follows: ldr , 222f 111: add , , pc .subsection 1 222: .long - (111b + 8) .previous This is allowed by the assembler because, unlike ordinary sections, subsections are combined into a single section into the object file, and so the label references are not true cross-section references that are visible as relocations. Note that we could even do something like add , pc, #(222f - 111f) & ~0xfff ldr , [, #(222f - 111f) & 0xfff] 111: add , , pc .subsection 1 222: .long - (111b + 8) .previous if it turns out that the 4 KB range of the ldr instruction is insufficient to reach the literal in the subsection, although this is currently not a problem (of the 98 objects built from .S files in a multi_v7_defconfig build, only 11 have .text sections that are over 1 KB, and the largest one [entry-armv.o] is 3308 bytes) Subsections have been available in binutils since 2004 at least, so they should not cause any issues with older toolchains. So use the above to implement the macros mov_l, adr_l, adrm_l (using ldm to load multiple literals at once), ldr_l and str_l, all of which will use movw/movt pairs on v7 and later CPUs, and use PC-relative literals otherwise. Signed-off-by: Ard Biesheuvel --- arch/arm/include/asm/assembler.h | 70 ++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index ad301f107dd2..cedf59a7f853 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -518,4 +518,74 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) #endif .endm +#ifdef CONFIG_THUMB2_KERNEL +#define ARM_PC_BIAS 4 +#else +#define ARM_PC_BIAS 8 +#endif + + .macro __adldst_l, op, reg, sym, tmp + .if __LINUX_ARM_ARCH__ < 7 + ldr \tmp, 111f + .subsection 1 + .align 2 +111: .long \sym - (222f + ARM_PC_BIAS) + .previous + .else + movw \tmp, #:lower16:\sym - (222f + ARM_PC_BIAS) + movt \tmp, #:upper16:\sym - (222f + ARM_PC_BIAS) + .endif +222:; .ifc \op, add + add \reg, \tmp, pc + .elseif CONFIG_THUMB2_KERNEL == 1 + add \tmp, \tmp, pc + \op \reg, [\tmp] + .else + \op \reg, [pc, \tmp] + .endif + .endm + + /* + * mov_l - move a constant value or [relocated] address into a register + */ + .macro mov_l, dst:req, imm:req + .if __LINUX_ARM_ARCH__ < 7 + ldr \dst, =\imm + .else + movw \dst, #:lower16:\imm + movt \dst, #:upper16:\imm + .endif + .endm + + /* + * adr_l - adr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + */ + .macro adr_l, dst:req, sym:req + __adldst_l add, \dst, \sym, \dst + .endm + + /* + * ldr_l - ldr pseudo-op with unlimited range + * + * @dst: destination register + * @sym: name of the symbol + */ + .macro ldr_l, dst:req, sym:req + __adldst_l ldr, \dst, \sym, \dst + .endm + + /* + * str_l - str pseudo-op with unlimited range + * + * @src: source register + * @sym: name of the symbol + * @tmp: mandatory scratch register + */ + .macro str_l, src:req, sym:req, tmp:req + __adldst_l str, \src, \sym, \tmp + .endm + #endif /* __ASM_ASSEMBLER_H__ */