From patchwork Tue Sep 12 20:37:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 9950121 X-Patchwork-Delegate: horms@verge.net.au Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AEFAF603F3 for ; Tue, 12 Sep 2017 21:06:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9F5A5290CC for ; Tue, 12 Sep 2017 21:06:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9E089290DC; Tue, 12 Sep 2017 21:06:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.4 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5B0F1290CE for ; Tue, 12 Sep 2017 21:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751442AbdILVF3 (ORCPT ); Tue, 12 Sep 2017 17:05:29 -0400 Received: from mail-lf0-f42.google.com ([209.85.215.42]:36530 "EHLO mail-lf0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751351AbdILVF2 (ORCPT ); Tue, 12 Sep 2017 17:05:28 -0400 Received: by mail-lf0-f42.google.com with SMTP id m199so29512266lfe.3 for ; Tue, 12 Sep 2017 14:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:message-id:user-agent:date:to:cc:subject:mime-version :content-disposition; bh=qknKDiI/NcxuGXmAqUp0W782cVUzTaQ8LVsiOmvQ90c=; b=qcfVoWUFmlaes7FM1pNNuF4KJSrVp+ejS0VsE3wiZL5g71HsQ+ZKqRvnMPMJcGG8LD eLZ4gU6e7I4axUfOXSiKc9n7Sk0GzRNcPe3IGNECZvv0y5C4gHxyhB3aMQpVO2WxdTyU I4YlOaHp2JCxHhM9WqEO04pLDCYT5jcNj6YGgdPY4edeSS7BLwZ37V7/NFVt5mitQv51 UEEogT3+TOB3oIMcTO0n56gv+tD2aOuIXztbHS5rIR+UhE0ZicF0uHXRqQ6wcrcDCIcf HQdHU49SOoHY0DnrmyFt34a3HH5ERJaFJyba9Ne5ucRBVcqK8B2+adYuk/jX7AtCRMW8 lYdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:message-id:user-agent:date:to:cc:subject :mime-version:content-disposition; bh=qknKDiI/NcxuGXmAqUp0W782cVUzTaQ8LVsiOmvQ90c=; b=e90O/5jLCLySF/s8h5bBCl5071+fULAkO4XmpYKeQ+KVSldU/zU81QpYycBtjB5s4S 7W4F2Prr5bw9eNAwHhg2DeDqMFXPdoaeR8VcHThomcvGYbD8C0srBJCVGZBuFfwWJ1xy BacaBI/rtsbAWgT/Q0bL4mP95FU+lBj0jSM9YxO3AjNRgQ/0gTjuunLsuZg9k9xGSUNC 0BMnSN3jFvexxnq1tBhhVm3rcgODGUtG0ozkhHlCpcnd+g2o688rE7YKwF5PSd8Z2wJP cxfcbBDBjYhPsjDweX0V1DUnlB98urrdSH/A1nu7Oc65VKNuUHCWbdD7o73/SGW2HfKz qJbQ== X-Gm-Message-State: AHPjjUiTSDa+aaIcz26WIH8fxvW9d+xcLk1qSGchONK8P7B37g5jQYW5 J49Pn/J1BEsT0YBnz0ojMw== X-Google-Smtp-Source: AOwi7QBkqINhXZLafkyfEsGm5jDfyoFur+EogfoOQ97h8oMFmdc3y7JzD8t/8guSetGxwdGgP7hlxA== X-Received: by 10.25.235.90 with SMTP id j87mr6444760lfh.249.1505250327134; Tue, 12 Sep 2017 14:05:27 -0700 (PDT) Received: from wasted.cogentembedded.com ([31.173.85.236]) by smtp.gmail.com with ESMTPSA id h27sm1286513lfb.80.2017.09.12.14.05.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Sep 2017 14:05:26 -0700 (PDT) From: Sergei Shtylyov X-Google-Original-From: "Sergei Shtylyov" Received: by wasted.cogentembedded.com (sSMTP sendmail emulation); Wed, 13 Sep 2017 00:05:23 +0300 Message-Id: <20170912210523.663877115@cogentembedded.com> User-Agent: quilt/0.64 Date: Tue, 12 Sep 2017 23:37:21 +0300 To: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Simon Horman , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Magnus Damm , linux-arm-kernel@lists.infradead.org, Vladimir Barinov , Sergei Shtylyov Subject: [PATCH 05/11] arm64: dts: renesas: initial R8A77970 SoC device tree MIME-Version: 1.0 Content-Disposition: inline; filename=arm64-dts-renesas-initial-R8A77970-SoC-device-tree.patch Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The initial R8A77970 SoC device tree including Cortex-A53 CPU, GIC, timer, CPG, RST, and SYSC. Based on the original (and large) patch by Daisuke Matsushita . Signed-off-by: Vladimir Barinov Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 126 ++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -0,0 +1,126 @@ +/* + * Device Tree Source for the r8a77970 SoC + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a77970"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc R8A77970_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A77970_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; +};