| Message ID | 20180307094046.4907-3-horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| State | Rejected |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Simon, On Wed, Mar 7, 2018 at 10:40 AM, Simon Horman <horms+renesas@verge.net.au> wrote: > Sort subnodes of the cpu node alphanumerically. > > This is part of an ongoing effort to provide consistent node > order in the DT of Renesas SoCs to improve maintainability. > > This should not have any run-time effect. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -34,6 +34,50 @@ > #address-cells = <1>; > #size-cells = <0>; > > + a53_0: cpu@100 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x100>; > + device_type = "cpu"; > + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; > + next-level-cache = <&L2_CA53>; > + enable-method = "psci"; > + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; > + operating-points-v2 = <&cluster1_opp>; > + }; [...] > a57_0: cpu@0 { > compatible = "arm,cortex-a57", "arm,armv8"; > reg = <0x0>; Given the CPU nodes do have reg properties and unit addresses, shouldn't they be sorted by these values, instead of alphabetically? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Wed, Mar 07, 2018 at 10:49:47AM +0100, Geert Uytterhoeven wrote: > Hi Simon, > > On Wed, Mar 7, 2018 at 10:40 AM, Simon Horman > <horms+renesas@verge.net.au> wrote: > > Sort subnodes of the cpu node alphanumerically. > > > > This is part of an ongoing effort to provide consistent node > > order in the DT of Renesas SoCs to improve maintainability. > > > > This should not have any run-time effect. > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > @@ -34,6 +34,50 @@ > > #address-cells = <1>; > > #size-cells = <0>; > > > > + a53_0: cpu@100 { > > + compatible = "arm,cortex-a53", "arm,armv8"; > > + reg = <0x100>; > > + device_type = "cpu"; > > + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; > > + next-level-cache = <&L2_CA53>; > > + enable-method = "psci"; > > + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; > > + operating-points-v2 = <&cluster1_opp>; > > + }; > > [...] > > > a57_0: cpu@0 { > > compatible = "arm,cortex-a57", "arm,armv8"; > > reg = <0x0>; > > Given the CPU nodes do have reg properties and unit addresses, shouldn't > they be sorted by these values, instead of alphabetically? Thanks, I agree. It looks like the nodes are already sorted according to that order so I withdraw this patch.
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 119c245b4ee2..d2ecb1dfa487 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -34,6 +34,50 @@ #address-cells = <1>; #size-cells = <0>; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + }; + a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; @@ -82,50 +126,6 @@ #cooling-cells = <2>; }; - a53_0: cpu@100 { - compatible = "arm,cortex-a53", "arm,armv8"; - reg = <0x100>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU0>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_1: cpu@101 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x101>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU1>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_2: cpu@102 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x102>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU2>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - - a53_3: cpu@103 { - compatible = "arm,cortex-a53","arm,armv8"; - reg = <0x103>; - device_type = "cpu"; - power-domains = <&sysc R8A7795_PD_CA53_CPU3>; - next-level-cache = <&L2_CA53>; - enable-method = "psci"; - clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>; - operating-points-v2 = <&cluster1_opp>; - }; - L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A7795_PD_CA57_SCU>;
Sort subnodes of the cpu node alphanumerically. This is part of an ongoing effort to provide consistent node order in the DT of Renesas SoCs to improve maintainability. This should not have any run-time effect. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 88 ++++++++++++++++---------------- 1 file changed, 44 insertions(+), 44 deletions(-)