| Message ID | 20180725143850.32985-2-chris.brandt@renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | serial: sh-sci: Add support for RZ/A2 | expand |
Hi Chris, On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt <chris.brandt@renesas.com> wrote: > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers. > Use the register area size to determine the spacing between register. > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > --- a/drivers/tty/serial/sh-sci.c > +++ b/drivers/tty/serial/sh-sci.c > @@ -2869,6 +2869,10 @@ static int sci_init_single(struct platform_device *dev, > port->regshift = 1; > } > > + if (p->regtype == SCIx_SH4_SCIF_REGTYPE) > + if (sci_port->reg_size >= 0x20) > + port->regshift = 1; > + So you have to be careful not to round up the reg size in DT to the next power of two (0x20), like you did for RZ/A1 (64 is used there). Note that while no SH board file uses SCIx_SH4_SCIF_REGTYPE, it is the default reg type for PORT_SCIF, so some board files may be affected. However, they all set reg_size to 0x100, so this change should be OK. Gr{oetje,eeting}s, Geert
Hi Geert, On Thursday, July 26, 2018, Geert Uytterhoeven wrote: > Hi Chris, > > On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt <chris.brandt@renesas.com> > wrote: > > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers. > > Use the register area size to determine the spacing between register. > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Thank you. > > + if (p->regtype == SCIx_SH4_SCIF_REGTYPE) > > + if (sci_port->reg_size >= 0x20) > > + port->regshift = 1; > > + > > So you have to be careful not to round up the reg size in DT to the next > power of two (0x20), like you did for RZ/A1 (64 is used there). Me???? It was Wolfram that committed the RZ/A1 DT scif code back in 2014 ;) Chris
Hi Chris, On Thu, Jul 26, 2018 at 2:14 PM Chris Brandt <Chris.Brandt@renesas.com> wrote: > On Thursday, July 26, 2018, Geert Uytterhoeven wrote: > > On Wed, Jul 25, 2018 at 4:39 PM Chris Brandt <chris.brandt@renesas.com> > > wrote: > > > Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers. > > > Use the register area size to determine the spacing between register. > > > > > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Thank you. > > > > + if (p->regtype == SCIx_SH4_SCIF_REGTYPE) > > > + if (sci_port->reg_size >= 0x20) > > > + port->regshift = 1; > > > + > > > > So you have to be careful not to round up the reg size in DT to the next > > power of two (0x20), like you did for RZ/A1 (64 is used there). > > Me???? > It was Wolfram that committed the RZ/A1 DT scif code back in 2014 ;) I stand corrected. (and RZLSP didn't use resources yet, but the old mapbase, so there are no sizes ;-) Gr{oetje,eeting}s, Geert
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index c181eb37f985..d9202ad1c9ca 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -315,15 +315,15 @@ static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { [SCIx_SH4_SCIF_REGTYPE] = { .regs = { [SCSMR] = { 0x00, 16 }, - [SCBRR] = { 0x04, 8 }, - [SCSCR] = { 0x08, 16 }, - [SCxTDR] = { 0x0c, 8 }, - [SCxSR] = { 0x10, 16 }, - [SCxRDR] = { 0x14, 8 }, - [SCFCR] = { 0x18, 16 }, - [SCFDR] = { 0x1c, 16 }, - [SCSPTR] = { 0x20, 16 }, - [SCLSR] = { 0x24, 16 }, + [SCBRR] = { 0x02, 8 }, + [SCSCR] = { 0x04, 16 }, + [SCxTDR] = { 0x06, 8 }, + [SCxSR] = { 0x08, 16 }, + [SCxRDR] = { 0x0a, 8 }, + [SCFCR] = { 0x0c, 16 }, + [SCFDR] = { 0x0e, 16 }, + [SCSPTR] = { 0x10, 16 }, + [SCLSR] = { 0x12, 16 }, }, .fifosize = 16, .overrun_reg = SCLSR, @@ -2869,6 +2869,10 @@ static int sci_init_single(struct platform_device *dev, port->regshift = 1; } + if (p->regtype == SCIx_SH4_SCIF_REGTYPE) + if (sci_port->reg_size >= 0x20) + port->regshift = 1; + /* * The UART port needs an IRQ value, so we peg this to the RX IRQ * for the multi-IRQ ports, which is where we are primarily
Some devices with SCIx_SH4_SCIF_REGTYPE have no space between registers. Use the register area size to determine the spacing between register. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> --- drivers/tty/serial/sh-sci.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-)