From patchwork Thu Jul 26 15:35:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10546063 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78A23157A for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6536E2B776 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 628192B7B7; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 07FED2B7C2 for ; Thu, 26 Jul 2018 15:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731798AbeGZQwr (ORCPT ); Thu, 26 Jul 2018 12:52:47 -0400 Received: from baptiste.telenet-ops.be ([195.130.132.51]:45400 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731822AbeGZQwq (ORCPT ); Thu, 26 Jul 2018 12:52:46 -0400 Received: from ramsan.of.borg ([84.194.111.163]) by baptiste.telenet-ops.be with bizsmtp id FTbN1y00L3XaVaC01TbN9m; Thu, 26 Jul 2018 17:35:22 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan.of.borg with esmtp (Exim 4.86_2) (envelope-from ) id 1fiiIU-0008Un-9D; Thu, 26 Jul 2018 17:35:22 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1fiiIU-0002d0-7O; Thu, 26 Jul 2018 17:35:22 +0200 From: Geert Uytterhoeven To: Michael Turquette , Stephen Boyd Cc: Takeshi Kihara , Sergei Shtylyov , linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2 09/11] clk: renesas: r8a77995: Correct RCLK handling Date: Thu, 26 Jul 2018 17:35:15 +0200 Message-Id: <20180726153517.10020-10-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726153517.10020-1-geert+renesas@glider.be> References: <20180726153517.10020-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car D3 has the RCLK Frequency Control Register (RCKCR), which determines the OSC and RINT predivider values, and selection of the RCLK clock source between RINT and the On-Chip Oscillator. Hence change the OSC and RINT clock definitions to use the RCKCR divider, and add the missing On-Chip Oscillator and RCLK clock source switching logic. Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman --- v2: - Add Reviewed-by, - Rename "r_int" to ".r", and "oco" to ".oco", as they are internal clocks. As Figure 8.1f "Block Diagram of CPG (R-Car D3)" shows 1/61 and 1/4 dividers after the On-Chip Oscillator, I assume the OCO runs at 8 MHz. --- drivers/clk/renesas/r8a77995-cpg-mssr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index ea4cafbe6e851aca..49e6a0de54916e2d 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -46,6 +46,8 @@ enum clk_ids { CLK_S3, CLK_SDSRC, CLK_SSPSRC, + CLK_RINT, + CLK_OCO, /* Module Clocks */ MOD_CLK_BASE @@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), + DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), + + DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), + /* Core Clock Outputs */ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), @@ -90,8 +96,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1), - DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1), - DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1), + + DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2), DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1), @@ -102,6 +108,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), + + DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4), }; static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {