From patchwork Tue Sep 18 01:45:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Niklas_S=C3=B6derlund?= X-Patchwork-Id: 10603659 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7C28015A6 for ; Tue, 18 Sep 2018 01:50:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 697F32A6F8 for ; Tue, 18 Sep 2018 01:50:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5DD0B2A721; Tue, 18 Sep 2018 01:50:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DD91B2A71F for ; Tue, 18 Sep 2018 01:50:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726990AbeIRHUI (ORCPT ); Tue, 18 Sep 2018 03:20:08 -0400 Received: from bin-mail-out-05.binero.net ([195.74.38.228]:32888 "EHLO bin-mail-out-05.binero.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726974AbeIRHUH (ORCPT ); Tue, 18 Sep 2018 03:20:07 -0400 X-Halon-ID: 1e626d97-bae5-11e8-ab18-005056917a89 Authorized-sender: niklas@soderlund.pp.se Received: from bismarck.berto.se (unknown [89.233.230.99]) by bin-vsp-out-01.atm.binero.net (Halon) with ESMTPA id 1e626d97-bae5-11e8-ab18-005056917a89; Tue, 18 Sep 2018 03:49:45 +0200 (CEST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Kieran Bingham , Laurent Pinchart , Jacopo Mondi , linux-media@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org, =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH 2/3] i2c: adv748x: configure number of lanes used for TXA CSI-2 transmitter Date: Tue, 18 Sep 2018 03:45:08 +0200 Message-Id: <20180918014509.6394-3-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> References: <20180918014509.6394-1-niklas.soderlund+renesas@ragnatech.se> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The driver fixed the TXA CSI-2 transmitter in 4-lane mode while it could operate using 1-, 2- and 4-lanes. Update the driver to support all modes the hardware does. The driver make use of large tables of static register/value writes when configuring the hardware, some writing to undocumented registers. Instead of creating 3 sets of the register tables for the different modes catch when the register containing NUM_LANES[2:0] is written to and inject the correct number of lanes. Signed-off-by: Niklas Söderlund --- drivers/media/i2c/adv748x/adv748x-core.c | 38 +++++++++++++++++++----- 1 file changed, 30 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/adv748x/adv748x-core.c b/drivers/media/i2c/adv748x/adv748x-core.c index a93f8ea89a228474..9a82cdf301bccb41 100644 --- a/drivers/media/i2c/adv748x/adv748x-core.c +++ b/drivers/media/i2c/adv748x/adv748x-core.c @@ -207,13 +207,23 @@ static int adv748x_write_regs(struct adv748x_state *state, const struct adv748x_reg_value *regs) { int ret; + u8 value; while (regs->page != ADV748X_PAGE_EOR) { if (regs->page == ADV748X_PAGE_WAIT) { msleep(regs->value); } else { + value = regs->value; + + /* + * Register 0x00 in TXA needs to bei injected with + * the number of CSI-2 lanes used to transmitt. + */ + if (regs->page == ADV748X_PAGE_TXA && regs->reg == 0x00) + value = (value & ~7) | state->txa.num_lanes; + ret = adv748x_write(state, regs->page, regs->reg, - regs->value); + value); if (ret < 0) { adv_err(state, "Error regs page: 0x%02x reg: 0x%02x\n", @@ -233,14 +243,18 @@ static int adv748x_write_regs(struct adv748x_state *state, static const struct adv748x_reg_value adv748x_power_up_txa_4lane[] = { - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ - {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0x00, 0xa0}, /* Set Auto DPHY Timing */ {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ - {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x20 },/* Power-up CSI-TX */ + {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ @@ -253,7 +267,10 @@ static const struct adv748x_reg_value adv748x_power_down_txa_4lane[] = { {ADV748X_PAGE_TXA, 0x31, 0x82}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0x1e, 0x00}, /* ADI Required Write */ - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_TXA, 0xc1, 0x3b}, /* ADI Required Write */ @@ -399,8 +416,10 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { /* Outputs Enabled */ {ADV748X_PAGE_IO, 0x10, 0xa0}, /* Enable 4-lane CSI Tx & Pixel Port */ - {ADV748X_PAGE_TXA, 0x00, 0x84}, /* Enable 4-lane MIPI */ - {ADV748X_PAGE_TXA, 0x00, 0xa4}, /* Set Auto DPHY Timing */ + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x80}, /* Enable n-lane MIPI */ + {ADV748X_PAGE_TXA, 0x00, 0xa0}, /* Set Auto DPHY Timing */ + {ADV748X_PAGE_TXA, 0xdb, 0x10}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xd6, 0x07}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xc4, 0x0a}, /* ADI Required Write */ @@ -412,7 +431,10 @@ static const struct adv748x_reg_value adv748x_init_txa_4lane[] = { {ADV748X_PAGE_TXA, 0x1e, 0x40}, /* ADI Required Write */ {ADV748X_PAGE_TXA, 0xda, 0x01}, /* i2c_mipi_pll_en - 1'b1 */ {ADV748X_PAGE_WAIT, 0x00, 0x02},/* delay 2 */ - {ADV748X_PAGE_TXA, 0x00, 0x24 },/* Power-up CSI-TX */ + + /* NOTE: NUM_LANES[2:0] in TXA register 0x00 is injected on write. */ + {ADV748X_PAGE_TXA, 0x00, 0x20 },/* Power-up CSI-TX */ + {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */ {ADV748X_PAGE_TXA, 0xc1, 0x2b}, /* ADI Required Write */ {ADV748X_PAGE_WAIT, 0x00, 0x01},/* delay 1 */