[v2,2/6] clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider

Commit Message

Simon Horman Jan. 30, 2019, 9:40 a.m. UTC

From: Takeshi Kihara <[e-mail]>

Add support for the Z2 clock divider for the R-Car E3 (r8a77990) SoC.
On this SoC the Z2 clock divider bits of the FRQCRC register are found at
bit[12:8] rather than the more common location bit[4:0].

Signed-off-by: Takeshi Kihara <[e-mail]>
[simon: reworked changelog]
Signed-off-by: Simon Horman <[e-mail]>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Patch

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index d50dd53121bb..db3b2efb40e9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -74,6 +74,7 @@  static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
 #define CPG_FRQCRB_KICK			BIT(31)
 #define CPG_FRQCRC			0x000000e0
 #define CPG_FRQCRC_ZFC_MASK		GENMASK(12, 8)
+#define CPG_FRQCRC_Z2FC_SFT_8_MASK	GENMASK(12, 8)
 #define CPG_FRQCRC_Z2FC_MASK		GENMASK(4, 0)
 
 struct cpg_z_clk {
@@ -365,6 +366,7 @@  static u32 cpg_quirks __initdata;
 #define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
 #define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
 #define SD_SKIP_FIRST	BIT(2)		/* Skip first clock in SD table */
+#define Z2FC_BIT_MASK_SFT_8	BIT(3)	/* Use Z2FC bit mask range to [12:8] */
 
 static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
 	void __iomem *base, const char *parent_name,
@@ -445,6 +447,10 @@  static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 		.soc_id = "r8a7796", .revision = "ES1.1",
 		.data = (void *)SD_SKIP_FIRST,
 	},
+	{
+		.soc_id = "r8a77990",
+		.data = (void *)Z2FC_BIT_MASK_SFT_8,
+	},
 	{ /* sentinel */ }
 };
 
@@ -572,6 +578,12 @@  struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 					  base, CPG_FRQCRC_ZFC_MASK, core->div);
 
 	case CLK_TYPE_GEN3_Z2:
+		if (cpg_quirks & Z2FC_BIT_MASK_SFT_8)
+			return cpg_z_clk_register(core->name,
+						  __clk_get_name(parent), base,
+						  CPG_FRQCRC_Z2FC_SFT_8_MASK,
+						  core->div);
+
 		return cpg_z_clk_register(core->name, __clk_get_name(parent),
 					  base, CPG_FRQCRC_Z2FC_MASK,
 					  core->div);