From patchwork Wed Jan 30 09:40:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788015 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CDE176C2 for ; Wed, 30 Jan 2019 09:40:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA1072E475 for ; Wed, 30 Jan 2019 09:40:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AD6112E47B; Wed, 30 Jan 2019 09:40:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 51F762E475 for ; Wed, 30 Jan 2019 09:40:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730337AbfA3Jky (ORCPT ); Wed, 30 Jan 2019 04:40:54 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jkx (ORCPT ); Wed, 30 Jan 2019 04:40:53 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 0DD9325BE91; Wed, 30 Jan 2019 20:40:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841245; bh=iEhMJruFvmlAneE/4lrBc0v0QceiwLpPvctbdnyfBLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gT7GPU5mElWCYCYjyg6rwrLayHl1fxF7RM/nGkdHLPiGV1Kgeke+jrM96b3u3wBGC 27X6N5PhN96JlKX2bpzazkwnrKp7jGhtRkwyxHnvfr4wrrN4/wBV3L0XMg0Pq6nEpi IL7lzKd5MOktxVsuIrD0PhpIei1ip/3dAkNQEFbc= Received: by reginn.horms.nl (Postfix, from userid 7100) id 3F4EE940461; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Takeshi Kihara , Simon Horman Subject: [PATCH v2 2/6] clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider Date: Wed, 30 Jan 2019 10:40:25 +0100 Message-Id: <20190130094029.9604-3-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Add support for the Z2 clock divider for the R-Car E3 (r8a77990) SoC. On this SoC the Z2 clock divider bits of the FRQCRC register are found at bit[12:8] rather than the more common location bit[4:0]. Signed-off-by: Takeshi Kihara [simon: reworked changelog] Signed-off-by: Simon Horman --- drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index d50dd53121bb..db3b2efb40e9 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -74,6 +74,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) +#define CPG_FRQCRC_Z2FC_SFT_8_MASK GENMASK(12, 8) #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) struct cpg_z_clk { @@ -365,6 +366,7 @@ static u32 cpg_quirks __initdata; #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ +#define Z2FC_BIT_MASK_SFT_8 BIT(3) /* Use Z2FC bit mask range to [12:8] */ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, void __iomem *base, const char *parent_name, @@ -445,6 +447,10 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { .soc_id = "r8a7796", .revision = "ES1.1", .data = (void *)SD_SKIP_FIRST, }, + { + .soc_id = "r8a77990", + .data = (void *)Z2FC_BIT_MASK_SFT_8, + }, { /* sentinel */ } }; @@ -572,6 +578,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, base, CPG_FRQCRC_ZFC_MASK, core->div); case CLK_TYPE_GEN3_Z2: + if (cpg_quirks & Z2FC_BIT_MASK_SFT_8) + return cpg_z_clk_register(core->name, + __clk_get_name(parent), base, + CPG_FRQCRC_Z2FC_SFT_8_MASK, + core->div); + return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK, core->div);