diff mbox series

[PATCH/RFT,v2,5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider

Message ID 20190130094029.9604-6-horms+renesas@verge.net.au (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: r8a77990: Add Z2 clock | expand

Commit Message

Simon Horman Jan. 30, 2019, 9:40 a.m. UTC
On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register,
which control the frequency division ratio for the Z2φ clock are
located at bit[12:8] rather than the more common location bit[4:0].

This change is made with reference to the User's Manual v0.61.

Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Biju Das Jan. 30, 2019, 9:43 a.m. UTC | #1
Hi Simon,

Thanks for the patch

> Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> divider
>
> On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> rather than the more common location bit[4:0].
>
> This change is made with reference to the User's Manual v0.61.
>
> Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> gen3-cpg.c
> index d21fdeb520e1..dfd2b9caeaf5 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> cpg_quirks_match[] __initconst = {
>  .soc_id = "r8a77990",
>  .data = (void *)Z2FC_BIT_MASK_SFT_8,
>  },
> +{
> +.soc_id = "r8a7745",
> +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> +},
>  { /* sentinel */ }
>  };


RZ/G2E  SoC id is r8a774c0.

Regards,
Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
Simon Horman Jan. 30, 2019, 10:10 a.m. UTC | #2
On Wed, Jan 30, 2019 at 09:43:31AM +0000, Biju Das wrote:
> Hi Simon,
> 
> Thanks for the patch
> 
> > Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> > divider
> >
> > On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> > control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> > rather than the more common location bit[4:0].
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> > gen3-cpg.c
> > index d21fdeb520e1..dfd2b9caeaf5 100644
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> > cpg_quirks_match[] __initconst = {
> >  .soc_id = "r8a77990",
> >  .data = (void *)Z2FC_BIT_MASK_SFT_8,
> >  },
> > +{
> > +.soc_id = "r8a7745",
> > +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> > +},
> >  { /* sentinel */ }
> >  };
> 
> 
> RZ/G2E  SoC id is r8a774c0.

Yikes! Silly me.
Fabrizio Castro Jan. 30, 2019, 6:51 p.m. UTC | #3
Hello Simon,

> From: Biju Das
> Sent: 30 January 2019 09:44
> Subject: RE: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider
>
> Hi Simon,
>
> Thanks for the patch
>
> > Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock
> > divider
> >
> > On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which
> > control the frequency division ratio for the Z2φ clock are located at bit[12:8]
> > rather than the more common location bit[4:0].
> >
> > This change is made with reference to the User's Manual v0.61.
> >
> > Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support")
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-
> > gen3-cpg.c
> > index d21fdeb520e1..dfd2b9caeaf5 100644
> > --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> > @@ -450,6 +450,10 @@ static const struct soc_device_attribute
> > cpg_quirks_match[] __initconst = {
> >  .soc_id = "r8a77990",
> >  .data = (void *)Z2FC_BIT_MASK_SFT_8,
> >  },
> > +{
> > +.soc_id = "r8a7745",
> > +.data = (void *)Z2FC_BIT_MASK_SFT_8,
> > +},
> >  { /* sentinel */ }
> >  };
>
>
> RZ/G2E  SoC id is r8a774c0.

+1

Cheers,
Fab

>
> Regards,
> Biju



Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index d21fdeb520e1..dfd2b9caeaf5 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -450,6 +450,10 @@  static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 		.soc_id = "r8a77990",
 		.data = (void *)Z2FC_BIT_MASK_SFT_8,
 	},
+	{
+		.soc_id = "r8a7745",
+		.data = (void *)Z2FC_BIT_MASK_SFT_8,
+	},
 	{ /* sentinel */ }
 };