From patchwork Wed Mar 20 10:21:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 10861309 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 363DC1908 for ; Wed, 20 Mar 2019 10:21:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F84D29A8E for ; Wed, 20 Mar 2019 10:21:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1400529ABD; Wed, 20 Mar 2019 10:21:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0440629A8E for ; Wed, 20 Mar 2019 10:21:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727577AbfCTKVq (ORCPT ); Wed, 20 Mar 2019 06:21:46 -0400 Received: from michel.telenet-ops.be ([195.130.137.88]:46484 "EHLO michel.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727616AbfCTKVq (ORCPT ); Wed, 20 Mar 2019 06:21:46 -0400 Received: from ramsan ([84.194.111.163]) by michel.telenet-ops.be with bizsmtp id qAMk1z0013XaVaC06AMkmq; Wed, 20 Mar 2019 11:21:44 +0100 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1h6YLv-0005Ft-V1; Wed, 20 Mar 2019 11:21:43 +0100 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1h6YLv-00052z-Ty; Wed, 20 Mar 2019 11:21:43 +0100 From: Geert Uytterhoeven To: Linus Walleij Cc: linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-sh@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v3 10/10] pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields Date: Wed, 20 Mar 2019 11:21:41 +0100 Message-Id: <20190320102141.19316-11-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190320102141.19316-1-geert+renesas@glider.be> References: <20190320102141.19316-1-geert+renesas@glider.be> Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a run-time check to the PINMUX_CFG_REG_VAR() macro, to ensure the number of provided enum IDs is correct. This cannot be done at build time, as the number of values depends on the variable-width fields in the config register. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven --- v3: - Reduce nr_enum_ids to u16, and move it into the existing padding hole, - Introduce SET_NR_ENUM_IDS() macro to reduce duplication and ifdef clutter, v2: - Extract into its own patch. --- drivers/pinctrl/sh-pfc/core.c | 6 ++++++ drivers/pinctrl/sh-pfc/sh_pfc.h | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 2ceed2f5ac08235b..3f989f5cb021ecbc 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -756,6 +756,12 @@ static void sh_pfc_check_cfg_reg(const char *drvname, drvname, cfg_reg->reg, rw, cfg_reg->reg_width); sh_pfc_errors++; } + + if (n != cfg_reg->nr_enum_ids) { + pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n", + drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n); + sh_pfc_errors++; + } } static void sh_pfc_check_info(const struct sh_pfc_soc_info *info) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index 31acde5032a0691a..2a6abeb62bab659b 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -111,6 +111,12 @@ struct pinmux_func { struct pinmux_cfg_reg { u32 reg; u8 reg_width, field_width; +#ifdef DEBUG + u16 nr_enum_ids; /* for variable width regs only */ +#define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, +#else +#define SET_NR_ENUM_IDS(n) +#endif const u16 *enum_ids; const u8 *var_field_width; }; @@ -151,6 +157,7 @@ struct pinmux_cfg_reg { #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ .reg = r, .reg_width = r_width, \ .var_field_width = (const u8 []) { f_widths, 0 }, \ + SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ .enum_ids = (const u16 []) { ids } struct pinmux_drive_reg_field {