| Message ID | 20190508173428.22054-8-jacopo+renesas@jmondi.org (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Kieran Bingham |
| Headers | show |
| Series | drm: rcar-du: Add CMM support to M3-W (plumbing only) | expand |
Hi Jacopo, Thank you for the patch. On Wed, May 08, 2019 at 07:34:26PM +0200, Jacopo Mondi wrote: > Enable the CMM units present in the group through the display unit > extensional function control group register DEFR7. > > Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> > --- > drivers/gpu/drm/rcar-du/rcar_du_group.c | 8 ++++++++ > drivers/gpu/drm/rcar-du/rcar_du_regs.h | 5 +++++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c > index 9eee47969e77..ce25e41b04bc 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c > @@ -147,6 +147,14 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) > > rcar_du_group_setup_pins(rgrp); > > + if (rgrp->cmms_mask) { > + u32 defr7 = DEFR7_CODE; > + defr7 |= rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0; > + defr7 |= rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0; > + > + rcar_du_group_write(rgrp, DEFR7, defr7); > + } > + I would guard this with the CMM feature bit instead of cmms_mask, in order to write the register with 0 if CMMs are not supported, just in case it maye have been written to another value by the boot loader (or before a warm reboot). Apart from that, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > if (rcdu->info->gen >= 2) { > rcar_du_group_setup_defr8(rgrp); > rcar_du_group_setup_didsr(rgrp); > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h > index bc87f080b170..fb9964949368 100644 > --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h > +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h > @@ -197,6 +197,11 @@ > #define DEFR6_MLOS1 (1 << 2) > #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) > > +#define DEFR7 0x000ec > +#define DEFR7_CODE (0x7779 << 16) > +#define DEFR7_CMME1 BIT(6) > +#define DEFR7_CMME0 BIT(4) > + > /* ----------------------------------------------------------------------------- > * R8A7790-only Control Registers > */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 9eee47969e77..ce25e41b04bc 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -147,6 +147,14 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp) rcar_du_group_setup_pins(rgrp); + if (rgrp->cmms_mask) { + u32 defr7 = DEFR7_CODE; + defr7 |= rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0; + defr7 |= rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0; + + rcar_du_group_write(rgrp, DEFR7, defr7); + } + if (rcdu->info->gen >= 2) { rcar_du_group_setup_defr8(rgrp); rcar_du_group_setup_didsr(rgrp); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h index bc87f080b170..fb9964949368 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h @@ -197,6 +197,11 @@ #define DEFR6_MLOS1 (1 << 2) #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) +#define DEFR7 0x000ec +#define DEFR7_CODE (0x7779 << 16) +#define DEFR7_CMME1 BIT(6) +#define DEFR7_CMME0 BIT(4) + /* ----------------------------------------------------------------------------- * R8A7790-only Control Registers */
Enable the CMM units present in the group through the display unit extensional function control group register DEFR7. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 8 ++++++++ drivers/gpu/drm/rcar-du/rcar_du_regs.h | 5 +++++ 2 files changed, 13 insertions(+)