diff mbox series

[v2,1/8] clk: renesas: rcar-gen2: Improve arithmetic divisions

Message ID 20190830134515.11925-2-geert+renesas@glider.be
State Mainlined
Commit 3e8c1d4cce6b679f4cfd81dfdbbf727f06986aa5
Delegated to: Geert Uytterhoeven
Headers show
Series clk: renesas: rcar-gen2/gen3: Switch to .determine_rate() | expand

Commit Message

Geert Uytterhoeven Aug. 30, 2019, 1:45 p.m. UTC
- Use div64_ul() instead of div_u64() if the divisor is unsigned long,
    to avoid truncation to 32-bit on 64-bit platforms,
  - Prefer ULL constant suffixes over casts to u64,
  - Prioritize multiplication over division, to increase accuracy.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2:
  - New.
---
 drivers/clk/renesas/rcar-gen2-cpg.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Niklas Söderlund Aug. 30, 2019, 9:42 p.m. UTC | #1
Hi Geert,

Thanks for your work.

On 2019-08-30 15:45:08 +0200, Geert Uytterhoeven wrote:
>   - Use div64_ul() instead of div_u64() if the divisor is unsigned long,
>     to avoid truncation to 32-bit on 64-bit platforms,
>   - Prefer ULL constant suffixes over casts to u64,
>   - Prioritize multiplication over division, to increase accuracy.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

> ---
> v2:
>   - New.
> ---
>  drivers/clk/renesas/rcar-gen2-cpg.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
> index f596a2dafcf4d8d1..c378505830f0bacc 100644
> --- a/drivers/clk/renesas/rcar-gen2-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen2-cpg.c
> @@ -72,10 +72,10 @@ static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
>  	if (!prate)
>  		prate = 1;
>  
> -	mult = div_u64((u64)rate * 32, prate);
> +	mult = div64_ul(rate * 32ULL, prate);
>  	mult = clamp(mult, 1U, 32U);
>  
> -	return *parent_rate / 32 * mult;
> +	return div_u64((u64)*parent_rate * mult, 32);
>  }
>  
>  static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
> @@ -86,7 +86,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>  	u32 val, kick;
>  	unsigned int i;
>  
> -	mult = div_u64((u64)rate * 32, parent_rate);
> +	mult = div64_ul(rate * 32ULL, parent_rate);
>  	mult = clamp(mult, 1U, 32U);
>  
>  	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index f596a2dafcf4d8d1..c378505830f0bacc 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -72,10 +72,10 @@  static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 	if (!prate)
 		prate = 1;
 
-	mult = div_u64((u64)rate * 32, prate);
+	mult = div64_ul(rate * 32ULL, prate);
 	mult = clamp(mult, 1U, 32U);
 
-	return *parent_rate / 32 * mult;
+	return div_u64((u64)*parent_rate * mult, 32);
 }
 
 static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -86,7 +86,7 @@  static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 	u32 val, kick;
 	unsigned int i;
 
-	mult = div_u64((u64)rate * 32, parent_rate);
+	mult = div64_ul(rate * 32ULL, parent_rate);
 	mult = clamp(mult, 1U, 32U);
 
 	if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)