| Message ID | 20190830134515.11925-4-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | e8adb3a0f74cf568030b7bd1f77d877e6f308d17 |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | clk: renesas: rcar-gen2/gen3: Switch to .determine_rate() | expand |
Hi Geert, Thanks for your patch. On 2019-08-30 15:45:10 +0200, Geert Uytterhoeven wrote: > The .set_rate() callback for the SD clocks is always called with a valid > clock rate, returned by .round_rate(). Hence there is no need to > iterate through the divider table twice: once to repeat the work done by > .round_rate(), and a second time to find the corresponding divider > entry. > > Just iterate once, looking for the divider that matches the passed clock > rate. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Clever :-) Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - No changes. > --- > drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c > index 3480284a08308134..9f457411984b1ca4 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, > } > > static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, > - unsigned long parent_rate) > + unsigned long parent_rate) > { > struct sd_clock *clock = to_sd_clock(hw); > - unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); > unsigned int i; > > for (i = 0; i < clock->div_num; i++) > - if (div == clock->div_table[i].div) > + if (rate == DIV_ROUND_CLOSEST(parent_rate, > + clock->div_table[i].div)) > break; > > if (i >= clock->div_num) > -- > 2.17.1 >
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 3480284a08308134..9f457411984b1ca4 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -339,14 +339,14 @@ static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate, } static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) + unsigned long parent_rate) { struct sd_clock *clock = to_sd_clock(hw); - unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate); unsigned int i; for (i = 0; i < clock->div_num; i++) - if (div == clock->div_table[i].div) + if (rate == DIV_ROUND_CLOSEST(parent_rate, + clock->div_table[i].div)) break; if (i >= clock->div_num)
The .set_rate() callback for the SD clocks is always called with a valid clock rate, returned by .round_rate(). Hence there is no need to iterate through the divider table twice: once to repeat the work done by .round_rate(), and a second time to find the corresponding divider entry. Just iterate once, looking for the divider that matches the passed clock rate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> --- v2: - No changes. --- drivers/clk/renesas/rcar-gen3-cpg.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)