diff mbox series

[1/3] pinctrl: sh-pfc: r8a77990: Rename AVB_AVTP_{MATCH,CAPTURE} pin functions

Message ID 20190904121658.2617-2-geert+renesas@glider.be (mailing list archive)
State Mainlined
Commit 05f841d2a92380d98cc2a3cc162bf068f154b2f1
Delegated to: Geert Uytterhoeven
Headers show
Series pinctrl: sh-pfc: r8a77990: Assorted fixes | expand

Commit Message

Geert Uytterhoeven Sept. 4, 2019, 12:16 p.m. UTC 
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2
register bit[23:20] value H'3 and register bit[27:24] value H'3 from
AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp.
AVB_AVTP_CAPTURE_A.

Update the R-Car E3 pin control driver to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Reword, reference errata]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Do we need a SH_PFC_PIN_GROUP_ALIAS() for backwards compatibility?
There are no users of the "avb_avtp_match_a" and "avb_avtp_capture_a"
pin groups in upstream DTS files, so I would say no.
---
 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 32 +++++++++++++--------------
 1 file changed, 16 insertions(+), 16 deletions(-)

Comments

Simon Horman Sept. 5, 2019, 8:59 a.m. UTC | #1 
On Wed, Sep 04, 2019 at 02:16:56PM +0200, Geert Uytterhoeven wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> 
> The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2
> register bit[23:20] value H'3 and register bit[27:24] value H'3 from
> AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp.
> AVB_AVTP_CAPTURE_A.

I think the trailing '_A' above is a typo.

That notwithstanding:

Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

> Update the R-Car E3 pin control driver to reflect this.
> 
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [geert: Reword, reference errata]
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Do we need a SH_PFC_PIN_GROUP_ALIAS() for backwards compatibility?
> There are no users of the "avb_avtp_match_a" and "avb_avtp_capture_a"
> pin groups in upstream DTS files, so I would say no.

Agreed.


> ---
>  drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 32 +++++++++++++--------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> index 2dfb8d9cfda126e4..2a6de2125bbf38b3 100644
> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> @@ -232,8 +232,8 @@
>  #define IP2_11_8	FM(AVB_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>  #define IP2_15_12	FM(BS_N)		FM(PWM0_A)		FM(AVB_MAGIC)		FM(VI4_CLK)		F_(0, 0)		FM(TX3_C)	F_(0, 0)	FM(VI5_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>  #define IP2_19_16	FM(RD_N)		FM(PWM1_A)		FM(AVB_LINK)		FM(VI4_FIELD)		F_(0, 0)		FM(RX3_C)	FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH_A)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE_A)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>  #define IP2_31_28	FM(A0)			FM(IRQ0)		FM(PWM2_A)		FM(MSIOF3_SS1_B)	FM(VI5_CLK_A)		FM(DU_CDE)	FM(HRX3_D)	FM(IERX)	FM(QSTB_QHE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>  #define IP3_3_0		FM(A1)			FM(IRQ1)		FM(PWM3_A)		FM(DU_DOTCLKIN1)	FM(VI5_DATA0_A)		FM(DU_DISP_CDE) FM(SDA6_B)	FM(IETX)	FM(QCPV_QDE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>  #define IP3_7_4		FM(A2)			FM(IRQ2)		FM(AVB_AVTP_PPS)	FM(VI4_CLKENB)		FM(VI5_DATA1_A)		FM(DU_DISP)	FM(SCL6_B)	F_(0, 0)	FM(QSTVB_QVE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> @@ -634,7 +634,7 @@ static const u16 pinmux_data[] = {
>  
>  	PINMUX_IPSR_GPSR(IP2_23_20,		RD_WR_N),
>  	PINMUX_IPSR_MSEL(IP2_23_20,		SCL7_A,		SEL_I2C7_0),
> -	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH_A),
> +	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH),
>  	PINMUX_IPSR_GPSR(IP2_23_20,		VI4_VSYNC_N),
>  	PINMUX_IPSR_GPSR(IP2_23_20,		TX5_B),
>  	PINMUX_IPSR_MSEL(IP2_23_20,		SCK3_C,		SEL_SCIF3_2),
> @@ -642,7 +642,7 @@ static const u16 pinmux_data[] = {
>  
>  	PINMUX_IPSR_GPSR(IP2_27_24,		EX_WAIT0),
>  	PINMUX_IPSR_MSEL(IP2_27_24,		SDA7_A,		SEL_I2C7_0),
> -	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE_A),
> +	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE),
>  	PINMUX_IPSR_GPSR(IP2_27_24,		VI4_HSYNC_N),
>  	PINMUX_IPSR_MSEL(IP2_27_24,		RX5_B,		SEL_SCIF5_1),
>  	PINMUX_IPSR_MSEL(IP2_27_24,		PWM6_A,		SEL_PWM6_0),
> @@ -1524,22 +1524,22 @@ static const unsigned int avb_avtp_pps_mux[] = {
>  	AVB_AVTP_PPS_MARK,
>  };
>  
> -static const unsigned int avb_avtp_match_a_pins[] = {
> -	/* AVB_AVTP_MATCH_A */
> +static const unsigned int avb_avtp_match_pins[] = {
> +	/* AVB_AVTP_MATCH */
>  	RCAR_GP_PIN(2, 24),
>  };
>  
> -static const unsigned int avb_avtp_match_a_mux[] = {
> -	AVB_AVTP_MATCH_A_MARK,
> +static const unsigned int avb_avtp_match_mux[] = {
> +	AVB_AVTP_MATCH_MARK,
>  };
>  
> -static const unsigned int avb_avtp_capture_a_pins[] = {
> -	/* AVB_AVTP_CAPTURE_A */
> +static const unsigned int avb_avtp_capture_pins[] = {
> +	/* AVB_AVTP_CAPTURE */
>  	RCAR_GP_PIN(2, 25),
>  };
>  
> -static const unsigned int avb_avtp_capture_a_mux[] = {
> -	AVB_AVTP_CAPTURE_A_MARK,
> +static const unsigned int avb_avtp_capture_mux[] = {
> +	AVB_AVTP_CAPTURE_MARK,
>  };
>  
>  /* - CAN ------------------------------------------------------------------ */
> @@ -3784,8 +3784,8 @@ static const struct {
>  		SH_PFC_PIN_GROUP(avb_phy_int),
>  		SH_PFC_PIN_GROUP(avb_mii),
>  		SH_PFC_PIN_GROUP(avb_avtp_pps),
> -		SH_PFC_PIN_GROUP(avb_avtp_match_a),
> -		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
> +		SH_PFC_PIN_GROUP(avb_avtp_match),
> +		SH_PFC_PIN_GROUP(avb_avtp_capture),
>  		SH_PFC_PIN_GROUP(can0_data),
>  		SH_PFC_PIN_GROUP(can1_data),
>  		SH_PFC_PIN_GROUP(can_clk),
> @@ -4061,8 +4061,8 @@ static const char * const avb_groups[] = {
>  	"avb_phy_int",
>  	"avb_mii",
>  	"avb_avtp_pps",
> -	"avb_avtp_match_a",
> -	"avb_avtp_capture_a",
> +	"avb_avtp_match",
> +	"avb_avtp_capture",
>  };
>  
>  static const char * const can0_groups[] = {
> -- 
> 2.17.1
>
Geert Uytterhoeven Sept. 10, 2019, 7:33 a.m. UTC | #2 
On Thu, Sep 5, 2019 at 10:59 AM Simon Horman <horms@verge.net.au> wrote:
> On Wed, Sep 04, 2019 at 02:16:56PM +0200, Geert Uytterhoeven wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > The Hardware Manual Errata for Rev. 1.50 of April 10, 2019 renamed IPSR2
> > register bit[23:20] value H'3 and register bit[27:24] value H'3 from
> > AVB_AVTP_MATCH_A resp. AVB_AVTP_CAPTURE_A to AVB_AVTP_MATCH resp.
> > AVB_AVTP_CAPTURE_A.
>
> I think the trailing '_A' above is a typo.
>
> That notwithstanding:
>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

Thanks, queueing in sh-pfc-for-v5.5 with the above fixed.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 2dfb8d9cfda126e4..2a6de2125bbf38b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -232,8 +232,8 @@ 
 #define IP2_11_8	FM(AVB_MDC)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_15_12	FM(BS_N)		FM(PWM0_A)		FM(AVB_MAGIC)		FM(VI4_CLK)		F_(0, 0)		FM(TX3_C)	F_(0, 0)	FM(VI5_CLK_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_19_16	FM(RD_N)		FM(PWM1_A)		FM(AVB_LINK)		FM(VI4_FIELD)		F_(0, 0)		FM(RX3_C)	FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH_A)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE_A)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_23_20	FM(RD_WR_N)		FM(SCL7_A)		FM(AVB_AVTP_MATCH)	FM(VI4_VSYNC_N)		FM(TX5_B)		FM(SCK3_C)	FM(PWM5_A)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2_27_24	FM(EX_WAIT0)		FM(SDA7_A)		FM(AVB_AVTP_CAPTURE)	FM(VI4_HSYNC_N)		FM(RX5_B)		FM(PWM6_A)	F_(0, 0)	F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP2_31_28	FM(A0)			FM(IRQ0)		FM(PWM2_A)		FM(MSIOF3_SS1_B)	FM(VI5_CLK_A)		FM(DU_CDE)	FM(HRX3_D)	FM(IERX)	FM(QSTB_QHE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3_3_0		FM(A1)			FM(IRQ1)		FM(PWM3_A)		FM(DU_DOTCLKIN1)	FM(VI5_DATA0_A)		FM(DU_DISP_CDE) FM(SDA6_B)	FM(IETX)	FM(QCPV_QDE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP3_7_4		FM(A2)			FM(IRQ2)		FM(AVB_AVTP_PPS)	FM(VI4_CLKENB)		FM(VI5_DATA1_A)		FM(DU_DISP)	FM(SCL6_B)	F_(0, 0)	FM(QSTVB_QVE)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -634,7 +634,7 @@  static const u16 pinmux_data[] = {
 
 	PINMUX_IPSR_GPSR(IP2_23_20,		RD_WR_N),
 	PINMUX_IPSR_MSEL(IP2_23_20,		SCL7_A,		SEL_I2C7_0),
-	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH_A),
+	PINMUX_IPSR_GPSR(IP2_23_20,		AVB_AVTP_MATCH),
 	PINMUX_IPSR_GPSR(IP2_23_20,		VI4_VSYNC_N),
 	PINMUX_IPSR_GPSR(IP2_23_20,		TX5_B),
 	PINMUX_IPSR_MSEL(IP2_23_20,		SCK3_C,		SEL_SCIF3_2),
@@ -642,7 +642,7 @@  static const u16 pinmux_data[] = {
 
 	PINMUX_IPSR_GPSR(IP2_27_24,		EX_WAIT0),
 	PINMUX_IPSR_MSEL(IP2_27_24,		SDA7_A,		SEL_I2C7_0),
-	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE_A),
+	PINMUX_IPSR_GPSR(IP2_27_24,		AVB_AVTP_CAPTURE),
 	PINMUX_IPSR_GPSR(IP2_27_24,		VI4_HSYNC_N),
 	PINMUX_IPSR_MSEL(IP2_27_24,		RX5_B,		SEL_SCIF5_1),
 	PINMUX_IPSR_MSEL(IP2_27_24,		PWM6_A,		SEL_PWM6_0),
@@ -1524,22 +1524,22 @@  static const unsigned int avb_avtp_pps_mux[] = {
 	AVB_AVTP_PPS_MARK,
 };
 
-static const unsigned int avb_avtp_match_a_pins[] = {
-	/* AVB_AVTP_MATCH_A */
+static const unsigned int avb_avtp_match_pins[] = {
+	/* AVB_AVTP_MATCH */
 	RCAR_GP_PIN(2, 24),
 };
 
-static const unsigned int avb_avtp_match_a_mux[] = {
-	AVB_AVTP_MATCH_A_MARK,
+static const unsigned int avb_avtp_match_mux[] = {
+	AVB_AVTP_MATCH_MARK,
 };
 
-static const unsigned int avb_avtp_capture_a_pins[] = {
-	/* AVB_AVTP_CAPTURE_A */
+static const unsigned int avb_avtp_capture_pins[] = {
+	/* AVB_AVTP_CAPTURE */
 	RCAR_GP_PIN(2, 25),
 };
 
-static const unsigned int avb_avtp_capture_a_mux[] = {
-	AVB_AVTP_CAPTURE_A_MARK,
+static const unsigned int avb_avtp_capture_mux[] = {
+	AVB_AVTP_CAPTURE_MARK,
 };
 
 /* - CAN ------------------------------------------------------------------ */
@@ -3784,8 +3784,8 @@  static const struct {
 		SH_PFC_PIN_GROUP(avb_phy_int),
 		SH_PFC_PIN_GROUP(avb_mii),
 		SH_PFC_PIN_GROUP(avb_avtp_pps),
-		SH_PFC_PIN_GROUP(avb_avtp_match_a),
-		SH_PFC_PIN_GROUP(avb_avtp_capture_a),
+		SH_PFC_PIN_GROUP(avb_avtp_match),
+		SH_PFC_PIN_GROUP(avb_avtp_capture),
 		SH_PFC_PIN_GROUP(can0_data),
 		SH_PFC_PIN_GROUP(can1_data),
 		SH_PFC_PIN_GROUP(can_clk),
@@ -4061,8 +4061,8 @@  static const char * const avb_groups[] = {
 	"avb_phy_int",
 	"avb_mii",
 	"avb_avtp_pps",
-	"avb_avtp_match_a",
-	"avb_avtp_capture_a",
+	"avb_avtp_match",
+	"avb_avtp_capture",
 };
 
 static const char * const can0_groups[] = {