From patchwork Wed Oct 23 12:29:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 11206507 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 72BA713BD for ; Wed, 23 Oct 2019 12:29:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 51795214B2 for ; Wed, 23 Oct 2019 12:29:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391312AbfJWM30 (ORCPT ); Wed, 23 Oct 2019 08:29:26 -0400 Received: from xavier.telenet-ops.be ([195.130.132.52]:39200 "EHLO xavier.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725947AbfJWM3Z (ORCPT ); Wed, 23 Oct 2019 08:29:25 -0400 Received: from ramsan ([84.194.98.4]) by xavier.telenet-ops.be with bizsmtp id H0VK2100A05gfCL010VKSW; Wed, 23 Oct 2019 14:29:23 +0200 Received: from rox.of.borg ([192.168.97.57]) by ramsan with esmtp (Exim 4.90_1) (envelope-from ) id 1iNFlP-0000Fs-7w; Wed, 23 Oct 2019 14:29:19 +0200 Received: from geert by rox.of.borg with local (Exim 4.90_1) (envelope-from ) id 1iNFlP-0003BL-6Y; Wed, 23 Oct 2019 14:29:19 +0200 From: Geert Uytterhoeven To: Magnus Damm , Rob Herring , Mark Rutland Cc: Philipp Zabel , Eugeniu Rosca , devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Geert Uytterhoeven Subject: [PATCH v2 5/5] dt-bindings: power: Add r8a77961 SYSC power domain definitions Date: Wed, 23 Oct 2019 14:29:11 +0200 Message-Id: <20191023122911.12166-6-geert+renesas@glider.be> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191023122911.12166-1-geert+renesas@glider.be> References: <20191023122911.12166-1-geert+renesas@glider.be> MIME-Version: 1.0 Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s Manual (Jul. 31, 2019). Signed-off-by: Geert Uytterhoeven Reviewed-by: Yoshihiro Shimoda Reviewed-by: Rob Herring --- v2: - Add Reviewed-by. --- include/dt-bindings/power/r8a77961-sysc.h | 32 +++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/dt-bindings/power/r8a77961-sysc.h diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h new file mode 100644 index 0000000000000000..7a3800996f7c0252 --- /dev/null +++ b/include/dt-bindings/power/r8a77961-sysc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77961_PD_CA57_CPU0 0 +#define R8A77961_PD_CA57_CPU1 1 +#define R8A77961_PD_CA53_CPU0 5 +#define R8A77961_PD_CA53_CPU1 6 +#define R8A77961_PD_CA53_CPU2 7 +#define R8A77961_PD_CA53_CPU3 8 +#define R8A77961_PD_CA57_SCU 12 +#define R8A77961_PD_CR7 13 +#define R8A77961_PD_A3VC 14 +#define R8A77961_PD_3DG_A 17 +#define R8A77961_PD_3DG_B 18 +#define R8A77961_PD_CA53_SCU 21 +#define R8A77961_PD_A3IR 24 +#define R8A77961_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77961_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */