diff mbox series

[PATCH/RFC,3/6] clk: renesas: r8a779a0: Add PFC/GPIO clocks

Message ID 20201019120614.22149-4-geert+renesas@glider.be
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series R-Car V3U GPIO support | expand

Commit Message

Geert Uytterhoeven Oct. 19, 2020, 12:06 p.m. UTC
Add the module clocks used by the Pin Function Controller (PFC) and
General Purpose Input/Output (GPIO) blocks, and their parent clock CP.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Untested on actual hardware.

Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Yoshihiro Shimoda Oct. 21, 2020, 7:40 a.m. UTC | #1
Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> 
> Add the module clocks used by the Pin Function Controller (PFC) and
> General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Untested on actual hardware.
> 
> Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda
Yoshihiro Shimoda Oct. 21, 2020, 8:07 a.m. UTC | #2
Hi Geert-san again,

> From: Yoshihiro Shimoda, Sent: Wednesday, October 21, 2020 4:41 PM
> 
> Hi Geert-san,
> 
> > From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> >
> > Add the module clocks used by the Pin Function Controller (PFC) and
> > General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Untested on actual hardware.
> >
> > Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> > clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> > V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> > the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
> 
> Thank you for the patch!
> 
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

I'm afraid but, since the upstream code doesn't have the following "vin3[567]"
lines, we should remove it from this patch. After fixed it,
you can use my Reviewed-by :)

>@@ -180,6 +181,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> 	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),
> 	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),
> 	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),

Best regards,
Yoshihiro Shimoda
Geert Uytterhoeven Oct. 21, 2020, 8:18 a.m. UTC | #3
Hi Shimoda-san,

On Wed, Oct 21, 2020 at 10:07 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Yoshihiro Shimoda, Sent: Wednesday, October 21, 2020 4:41 PM
> > > From: Geert Uytterhoeven, Sent: Monday, October 19, 2020 9:06 PM
> > >
> > > Add the module clocks used by the Pin Function Controller (PFC) and
> > > General Purpose Input/Output (GPIO) blocks, and their parent clock CP.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > ---
> > > Untested on actual hardware.
> > >
> > > Note that the BSP uses MAIN instead of EXTAL, just like for the CBFUSA
> > > clock.  However, according to Figure 8.1.1 ("Block Diagram of CPG (R-Car
> > > V3U-AD)") in the R-Car V3U Series User's Manual Rev. 0.5, the parent of
> > > the CP clock is EXTAL, which matches earlier R-Car Gen3 SoCs.
> >
> > Thank you for the patch!
> >
> > Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> I'm afraid but, since the upstream code doesn't have the following "vin3[567]"
> lines, we should remove it from this patch. After fixed it,
> you can use my Reviewed-by :)

Right, I had marked Jacopo's VIN clock patch for application to
renesas-clk-for-v5.11, but haven't actually done that, only in my local
tree.

But probably it does make sense to reorder the patches, and apply the
GPIO one first.

> >@@ -180,6 +181,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
> >       DEF_MOD("vin35",        827,    R8A779A0_CLK_S1D1),
> >       DEF_MOD("vin36",        828,    R8A779A0_CLK_S1D1),
> >       DEF_MOD("vin37",        829,    R8A779A0_CLK_S1D1),

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 968be8206a480015..9d414ad9dd4469d2 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -130,6 +130,7 @@  static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_FIXED("icud2",	R8A779A0_CLK_ICUD2,	CLK_PLL5_DIV4,	4, 1),
 	DEF_FIXED("vcbus",	R8A779A0_CLK_VCBUS,	CLK_PLL5_DIV4,	1, 1),
 	DEF_FIXED("cbfusa",	R8A779A0_CLK_CBFUSA,	CLK_EXTAL,	2, 1),
+	DEF_FIXED("cp",		R8A779A0_CLK_CP,	CLK_EXTAL,	2, 1),
 
 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
@@ -180,6 +181,10 @@  static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
 	DEF_MOD("vin35",	827,	R8A779A0_CLK_S1D1),
 	DEF_MOD("vin36",	828,	R8A779A0_CLK_S1D1),
 	DEF_MOD("vin37",	829,	R8A779A0_CLK_S1D1),
+	DEF_MOD("pfc0",		915,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc1",		916,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc2",		917,	R8A779A0_CLK_CP),
+	DEF_MOD("pfc3",		918,	R8A779A0_CLK_CP),
 };
 
 static spinlock_t cpg_lock;