Message ID | 20201019124258.4574-5-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Accepted |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Optimize pinctrl image size for RZ/G SoC's | expand |
On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's. > Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is > disabled in the defconfig. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-pinctrl-for-v5.11, with comments added to the #endifs where appropriate. Gr{oetje,eeting}s, Geert
On Thu, Oct 22, 2020 at 2:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's. > > Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is Ooops, R8A77990, twice. Will fix while applying. > > disabled in the defconfig. Gr{oetje,eeting}s, Geert
Hi Geert, > Subject: Re: [PATCH 4/6] pinctrl: renesas: r8a77990: Optimize pinctrl image > size for R8A774C0 > > On Thu, Oct 22, 2020 at 2:04 PM Geert Uytterhoeven <geert@linux- > m68k.org> wrote: > > On Mon, Oct 19, 2020 at 2:43 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > > This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's. > > > Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC > > > is > > Ooops, R8A77990, twice. Will fix while applying. Thanks, I didn't spot this. Regards, Biju > > > disabled in the defconfig. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index aed04a4c6116..47d57cf88011 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -1593,6 +1593,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -1785,6 +1786,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -3761,7 +3763,9 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[247]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_pin_group automotive[21]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a), @@ -4012,6 +4016,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clk_a), SH_PFC_PIN_GROUP(vin5_clk_b), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4035,6 +4040,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } +#endif }; static const char * const audio_clk_groups[] = { @@ -4088,6 +4094,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4120,6 +4127,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif static const char * const du_groups[] = { "du_rgb666", @@ -4460,7 +4468,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[47]; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -4511,12 +4521,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A77990 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } +#endif }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {
This driver supports both RZ/G2E and R-Car E3(R8A774C0) SoC's. Optimize pinctrl image size for RZ/G2E, when R-Car E3(R8A774C0) SoC is disabled in the defconfig. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/pinctrl/renesas/pfc-r8a77990.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)