| Message ID | 20201110142058.36393-4-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | mmc: renesas_sdhi: reset SCC only when available | expand |
Hi Wolfram, Thanks for your patch. On 2020-11-10 15:20:57 +0100, Wolfram Sang wrote: > The SCC pointer is currently filled whenever the SoC is Gen2+. This is > wrong because there is a Gen2-variant without SCC (SDHI_VER_GEN2_SDR50). > We have been lucky because the writes to unintended registers have not > caused problems so far. But further refactoring work exposed the > problem. So, move the pointer initialization to the place where we know > that the SDHI instance supports tuning. And also populate the 'reset' > pointer unconditionally to make sure the interrupt enable register is > always properly set for Gen2+. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > drivers/mmc/host/renesas_sdhi_core.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c > index 17ebaa324ca1..4a1ed5bf216c 100644 > --- a/drivers/mmc/host/renesas_sdhi_core.c > +++ b/drivers/mmc/host/renesas_sdhi_core.c > @@ -1007,11 +1007,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, > host->ops.start_signal_voltage_switch = > renesas_sdhi_start_signal_voltage_switch; > host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; > - > - if (of_data && of_data->scc_offset) { > - priv->scc_ctl = host->ctl + of_data->scc_offset; > - host->reset = renesas_sdhi_reset; > - } > + host->reset = renesas_sdhi_reset; > } > > /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ > @@ -1091,6 +1087,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, > if (!hit) > dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); > > + priv->scc_ctl = host->ctl + of_data->scc_offset; > host->check_retune = renesas_sdhi_check_scc_error; > host->ops.execute_tuning = renesas_sdhi_execute_tuning; > host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; > -- > 2.28.0 >
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index 17ebaa324ca1..4a1ed5bf216c 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -1007,11 +1007,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->ops.start_signal_voltage_switch = renesas_sdhi_start_signal_voltage_switch; host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; - - if (of_data && of_data->scc_offset) { - priv->scc_ctl = host->ctl + of_data->scc_offset; - host->reset = renesas_sdhi_reset; - } + host->reset = renesas_sdhi_reset; } /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ @@ -1091,6 +1087,7 @@ int renesas_sdhi_probe(struct platform_device *pdev, if (!hit) dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); + priv->scc_ctl = host->ctl + of_data->scc_offset; host->check_retune = renesas_sdhi_check_scc_error; host->ops.execute_tuning = renesas_sdhi_execute_tuning; host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning;
The SCC pointer is currently filled whenever the SoC is Gen2+. This is wrong because there is a Gen2-variant without SCC (SDHI_VER_GEN2_SDR50). We have been lucky because the writes to unintended registers have not caused problems so far. But further refactoring work exposed the problem. So, move the pointer initialization to the place where we know that the SDHI instance supports tuning. And also populate the 'reset' pointer unconditionally to make sure the interrupt enable register is always properly set for Gen2+. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- drivers/mmc/host/renesas_sdhi_core.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)