diff mbox series

[3/5] arm64: dts: renesas: r8a779a0: Add RWDT node

Message ID 20201218173731.12839-4-wsa+renesas@sang-engineering.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series v3u: add support for RWDT | expand

Commit Message

Wolfram Sang Dec. 18, 2020, 5:37 p.m. UTC 
From: Hoang Vo <hoang.vo.eb@renesas.com>

Add a device node for the Watchdog Timer (WDT) controller on the
R8A779A0 SoC.

Signed-off-by: Hoang Vo <hoang.vo.eb@renesas.com>
[wsa: rebased to mainline]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Wolfram Sang Dec. 21, 2020, 2:51 p.m. UTC | #1 
> +			reg = <0 0xe6020000 0 0x0c>;

I just understood that we sort by reg value and not by name. So, this
needs to be moved to another place then.
Geert Uytterhoeven Dec. 22, 2020, 9:13 a.m. UTC | #2 
On Fri, Dec 18, 2020 at 6:37 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Hoang Vo <hoang.vo.eb@renesas.com>
>
> Add a device node for the Watchdog Timer (WDT) controller on the
> R8A779A0 SoC.
>
> Signed-off-by: Hoang Vo <hoang.vo.eb@renesas.com>
> [wsa: rebased to mainline]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.12 (with sort order fixed).

> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -85,6 +85,16 @@ rst: reset-controller@e6160000 {
>                         reg = <0 0xe6160000 0 0x4000>;
>                 };
>
> +               rwdt: watchdog@e6020000 {
> +                       compatible = "renesas,r8a779a0-wdt",
> +                                    "renesas,rcar-gen3-wdt";
> +                       reg = <0 0xe6020000 0 0x0c>;
> +                       clocks = <&cpg CPG_MOD 907>;
> +                       power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> +                       resets = <&cpg 907>;
> +                       status = "disabled";

No interrupts property? ;-)
As we don't have it described yet for the other R-Car Gen3 SoCs, I
suggest we do that in one batch...

> +               };
> +
>                 sysc: system-controller@e6180000 {
>                         compatible = "renesas,r8a779a0-sysc";
>                         reg = <0 0xe6180000 0 0x4000>;

Gr{oetje,eeting}s,

                        Geert
Wolfram Sang Dec. 22, 2020, 9:16 a.m. UTC | #3 
> No interrupts property? ;-)
> As we don't have it described yet for the other R-Car Gen3 SoCs, I
> suggest we do that in one batch...

Yes, I'll try to find some time for this as a seperate series.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 6cf77ce9aa93..1ca500f55096 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -85,6 +85,16 @@  rst: reset-controller@e6160000 {
 			reg = <0 0xe6160000 0 0x4000>;
 		};
 
+		rwdt: watchdog@e6020000 {
+			compatible = "renesas,r8a779a0-wdt",
+				     "renesas,rcar-gen3-wdt";
+			reg = <0 0xe6020000 0 0x0c>;
+			clocks = <&cpg CPG_MOD 907>;
+			power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+			resets = <&cpg 907>;
+			status = "disabled";
+		};
+
 		sysc: system-controller@e6180000 {
 			compatible = "renesas,r8a779a0-sysc";
 			reg = <0 0xe6180000 0 0x4000>;