| Message ID | 20201221165448.27312-2-uli+renesas@fpond.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | pinctrl: renesas: basic R8A779A0 (V3U) support | expand |
Hi Uli, On Mon, Dec 21, 2020 at 5:55 PM Ulrich Hecht <uli+renesas@fpond.eu> wrote: > The V3U SoC has several unlock registers, one per register group. They > reside at offset zero in each 0x200 bytes-sized block. > > To avoid adding yet another table to the PFC implementation, this > patch adds the option to specify an address mask instead of the fixed > address in sh_pfc_soc_info::unlock_reg. > > Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> My comments for v1 are still valid: Perhaps a comment should be added to sh_pfc_soc_info.unlock_reg, to document this dual behavior? Or should we just always use masking, as that seems to be suited for all SoCs using unlock_reg? Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 2cc457279345..4cd95e220900 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -175,13 +175,25 @@ u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg) return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32); } -void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data) { - if (pfc->info->unlock_reg) - sh_pfc_write_raw_reg( - sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, - ~data); + u32 unlock; + + if (!pfc->info->unlock_reg) + return; + if (pfc->info->unlock_reg >= 0x80000000UL) + unlock = pfc->info->unlock_reg; + else + /* unlock_reg is a mask */ + unlock = reg & ~pfc->info->unlock_reg; + + sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data); +} + +void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data) +{ + sh_pfc_unlock_reg(pfc, reg, data); sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data); } @@ -227,11 +239,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc, data &= mask; data |= value; - if (pfc->info->unlock_reg) - sh_pfc_write_raw_reg( - sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, - ~data); - + sh_pfc_unlock_reg(pfc, crp->reg, data); sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); }
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> --- drivers/pinctrl/renesas/core.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)