diff mbox series

watchdog: renesas_wdt: add grace period before rebooting

Message ID 20210118094558.36814-1-wsa+renesas@sang-engineering.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series watchdog: renesas_wdt: add grace period before rebooting | expand

Commit Message

Wolfram Sang Jan. 18, 2021, 9:45 a.m. UTC
arm64 does not have a grace period after calling reset handlers. It is
rightfully assumed that watchdog drivers should wait because they know
the time needed. Implement this for the Renesas watchdog driver.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/watchdog/renesas_wdt.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Guenter Roeck Jan. 18, 2021, 4:03 p.m. UTC | #1
On 1/18/21 1:45 AM, Wolfram Sang wrote:
> arm64 does not have a grace period after calling reset handlers. It is
> rightfully assumed that watchdog drivers should wait because they know
> the time needed. Implement this for the Renesas watchdog driver.
> 
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Reviewed-by: Guenter Roeck <linux@oeck-us.net>

> ---
>  drivers/watchdog/renesas_wdt.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
> index d2b5074bca65..5791198960e6 100644
> --- a/drivers/watchdog/renesas_wdt.c
> +++ b/drivers/watchdog/renesas_wdt.c
> @@ -151,6 +151,9 @@ static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
>  
>  	rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
>  
> +	/* wait 2 cycles, so watchdog will trigger */
> +	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
> +
>  	return 0;
>  }
>  
>
diff mbox series

Patch

diff --git a/drivers/watchdog/renesas_wdt.c b/drivers/watchdog/renesas_wdt.c
index d2b5074bca65..5791198960e6 100644
--- a/drivers/watchdog/renesas_wdt.c
+++ b/drivers/watchdog/renesas_wdt.c
@@ -151,6 +151,9 @@  static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
 
 	rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
 
+	/* wait 2 cycles, so watchdog will trigger */
+	udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
+
 	return 0;
 }