diff mbox series

[v3,3/3] mmc: renesas_sdhi: do hard reset if possible

Message ID 20210317091622.31890-4-wsa+renesas@sang-engineering.com (mailing list archive)
State Accepted
Delegated to: Geert Uytterhoeven
Headers show
Series mmc: renesas_sdhi: reset via reset controller | expand

Commit Message

Wolfram Sang March 17, 2021, 9:16 a.m. UTC
All recent SDHI instances can be reset via the reset controller. If one
is found, use it instead of the open coded reset. This is to get a
future-proof sane reset state.

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/mmc/host/Kconfig             |  1 +
 drivers/mmc/host/renesas_sdhi.h      |  2 ++
 drivers/mmc/host/renesas_sdhi_core.c | 17 ++++++++++++++++-
 3 files changed, 19 insertions(+), 1 deletion(-)

Comments

Geert Uytterhoeven April 28, 2021, 2:36 p.m. UTC | #1
Hi Wolfram,

On Wed, Mar 17, 2021 at 10:17 AM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> All recent SDHI instances can be reset via the reset controller. If one
> is found, use it instead of the open coded reset. This is to get a
> future-proof sane reset state.
>
> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch, which is now commit b4d86f37eacb7246 ("mmc:
renesas_sdhi: do hard reset if possible") in mmc/next.

This breaks SDHI on koelsch (R-Car M2-W).
In v5.10, v5.11, and v512, it works fine:

    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    mmc0: new ultra high speed SDR104 SDHC card at address aaaa
    mmcblk0: mmc0:aaaa SM32G 29.7 GiB
      mmcblk0: p1

Note that I do see one timeout during identification.

After b4d86f37eacb7246 (bisected), it fails:

    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    [...]
    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    mmc0: tuning execution failed: -5
    mmc0: error -5 whilst initialising SD card
    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    [...]

Given the single timeout I see with older kernels, the issue may be that the
harder reset causes that timeout to repeat ad infinitum?

With renesas-drivers-2021-04-27-v5.12, I saw various different timeouts:

    sh_mobile_sdhi ee100000.mmc: timeout waiting for hardware interrupt (CMD19)
    sh_mobile_sdhi ee140000.mmc: timeout waiting for hardware interrupt (CMD0)
    sh_mobile_sdhi ee140000.mmc: timeout waiting for hardware interrupt (CMD5)
    sh_mobile_sdhi ee140000.mmc: timeout waiting for hardware interrupt (CMD52)
    sh_mobile_sdhi ee140000.mmc: timeout waiting for hardware interrupt (CMD55)
    sh_mobile_sdhi ee140000.mmc: timeout waiting for hardware interrupt (CMD8)

(ee100000 is the SD104 slot, ee140000 is the SDR50 slot).

The card is a brand new SanDisk Extreme 32GB A1 microSD card in the
microSD adapter that came with the card (Conrad 1553726).

On R-Car H3 ES2.0 (Salvator-XS), the card works fine, without any timeouts:

    mmc1: new ultra high speed SDR104 SDHC card at address aaaa
    mmcblk1: mmc1:aaaa SM32G 29.7 GiB
     mmcblk1: p1

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b236dfe2e879..2f6bc19d0e40 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -707,6 +707,7 @@  config MMC_SDHI
 	tristate "Renesas SDHI SD/SDIO controller support"
 	depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
 	select MMC_TMIO_CORE
+	select RESET_CONTROLLER if ARCH_RENESAS
 	help
 	  This provides support for the SDHI SD/SDIO controller found in
 	  Renesas SuperH, ARM and ARM64 based SoCs
diff --git a/drivers/mmc/host/renesas_sdhi.h b/drivers/mmc/host/renesas_sdhi.h
index cb962c7883dc..53eded81a53e 100644
--- a/drivers/mmc/host/renesas_sdhi.h
+++ b/drivers/mmc/host/renesas_sdhi.h
@@ -70,6 +70,8 @@  struct renesas_sdhi {
 	DECLARE_BITMAP(smpcmp, BITS_PER_LONG);
 	unsigned int tap_num;
 	unsigned int tap_set;
+
+	struct reset_control *rstc;
 };
 
 #define host_to_priv(host) \
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index db753829eaf6..d36181b6f687 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -20,6 +20,7 @@ 
 
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/iopoll.h>
 #include <linux/kernel.h>
 #include <linux/mfd/tmio.h>
 #include <linux/mmc/host.h>
@@ -32,6 +33,7 @@ 
 #include <linux/platform_device.h>
 #include <linux/pm_domain.h>
 #include <linux/regulator/consumer.h>
+#include <linux/reset.h>
 #include <linux/sh_dma.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
@@ -572,10 +574,19 @@  static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sd
 static void renesas_sdhi_reset(struct tmio_mmc_host *host)
 {
 	struct renesas_sdhi *priv = host_to_priv(host);
+	int ret;
 	u16 val;
 
-	if (priv->scc_ctl)
+	if (priv->rstc) {
+		reset_control_reset(priv->rstc);
+		/* Unknown why but without polling reset status, it will hang */
+		read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100,
+				  false, priv->rstc);
+		priv->needs_adjust_hs400 = false;
+		renesas_sdhi_set_clock(host, host->clk_cache);
+	} else if (priv->scc_ctl) {
 		renesas_sdhi_scc_reset(host, priv);
+	}
 
 	sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, TMIO_MASK_ALL_RCAR2);
 
@@ -1081,6 +1092,10 @@  int renesas_sdhi_probe(struct platform_device *pdev,
 	if (ret)
 		goto efree;
 
+	priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(priv->rstc))
+		return PTR_ERR(priv->rstc);
+
 	ver = sd_ctrl_read16(host, CTL_VERSION);
 	/* GEN2_SDR104 is first known SDHI to use 32bit block count */
 	if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX)