diff mbox series

[v2,02/11] drivers: clk: renesas: r9a07g044-cpg: Add USB clocks

Message ID 20210621093943.12143-3-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add USB2.0 support. | expand

Commit Message

Biju Das June 21, 2021, 9:39 a.m. UTC 
Add clock entries for USB PHY control, USB2.0 host and device.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
 * Reworked on clock/reset definitions
---
 drivers/clk/renesas/r9a07g044-cpg.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bdede1d28086..0a17cf7cb548 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -108,6 +108,18 @@  static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 	DEF_MOD("dmac_pclk",	R9A07G044_DMAC_PCLK,
 				CLK_P1_DIV2,
 				0x52c, BIT(1), BIT(1)),
+	DEF_MOD("usb_pclk",	R9A07G044_USB_PCLK,
+				R9A07G044_CLK_P1,
+				0x578, BIT(3), BIT(3)),
+	DEF_MOD("usb_function",	R9A07G044_USB_U2P_EXR_CPUCLK,
+				R9A07G044_CLK_P1,
+				0x578, BIT(2), BIT(2)),
+	DEF_MOD("usb_host1",	R9A07G044_USB_U2H1_HCLK,
+				R9A07G044_CLK_P1,
+				0x578, BIT(1), BIT(1)),
+	DEF_MOD("usb_host0",	R9A07G044_USB_U2H0_HCLK,
+				R9A07G044_CLK_P1,
+				0x578, BIT(0), BIT(0)),
 	DEF_MOD("i2c0",		R9A07G044_I2C0_PCLK,
 				R9A07G044_CLK_P0,
 				0x580, BIT(0), BIT(0)),