[5/6] clk: renesas: r9a07g044-cpg: Add clock and reset entries for CANFD

Commit Message

Lad Prabhakar July 15, 2021, 6:21 p.m. UTC

Add clock and reset entries for CANFD in CPG driver.

Signed-off-by: Lad Prabhakar <[e-mail]>
Reviewed-by: Biju Das <[e-mail]>
---
 drivers/clk/renesas/r9a07g044-cpg.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Geert Uytterhoeven July 16, 2021, 7:55 a.m. UTC | #1

On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar
<[e-mail]> wrote:
> Add clock and reset entries for CANFD in CPG driver.
>
> Signed-off-by: Lad Prabhakar <[e-mail]>
> Reviewed-by: Biju Das <[e-mail]>

Reviewed-by: Geert Uytterhoeven <[e-mail]>
i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

Patch

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0876df9c286d..78f0efb19af8 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -141,6 +141,8 @@  static struct rzg2l_mod_clk r9a07g044_mod_clks[] = {
 				0x584, 4),
 	DEF_MOD("sci0",		R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0,
 				0x588, 0),
+	DEF_MOD("canfd",	R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0,
+				0x594, 0),
 	DEF_MOD("gpio",		R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK,
 				0x598, 0),
 };
@@ -169,6 +171,8 @@  static struct rzg2l_reset r9a07g044_resets[] = {
 	DEF_RST(R9A07G044_SCIF3_RST_SYSTEM_N, 0x884, 3),
 	DEF_RST(R9A07G044_SCIF4_RST_SYSTEM_N, 0x884, 4),
 	DEF_RST(R9A07G044_SCI0_RST, 0x888, 0),
+	DEF_RST(R9A07G044_CANFD_RSTP_N, 0x894, 0),
+	DEF_RST(R9A07G044_CANFD_RSTC_N, 0x894, 1),
 	DEF_RST(R9A07G044_GPIO_RSTN, 0x898, 0),
 	DEF_RST(R9A07G044_GPIO_PORT_RESETN, 0x898, 1),
 	DEF_RST(R9A07G044_GPIO_SPARE_RESETN, 0x898, 2),