Message ID | 20210722141351.13668-4-biju.das.jz@bp.renesas.com (mailing list archive) |
---|---|
State | Superseded |
Delegated to: | Geert Uytterhoeven |
Headers | show |
Series | Add Gigabit Ethernet driver support | expand |
Hi Biju, On Thu, Jul 22, 2021 at 4:14 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > Ethernet reference clock can be sourced from PLL5_2 or PLL6_2. Add support > for ethernet source clock selection using SEL_PLL_6_2 mux. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/drivers/clk/renesas/r9a07g044-cpg.c > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > @@ -35,8 +35,10 @@ enum clk_ids { > CLK_PLL3_DIV4, > CLK_PLL4, > CLK_PLL5, > + CLK_PLL5_2, Why do you need this? We already have CLK_PLL5_DIV2? > CLK_PLL5_DIV2, > CLK_PLL6, > + CLK_PLL6_DIV2, > CLK_P1_DIV2, > > /* Module Clocks */ > @@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = { > {0, 0}, > }; > > +/* Mux clock tables */ > +static const char * const sel_pll6_2[] = { ".pll6_2_div2", ".pll5_2_div2" }; ".pll6_div2", ".pll5_div2" > + > static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > /* External Clock Inputs */ > DEF_INPUT("extal", CLK_EXTAL), > @@ -64,6 +69,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), > DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), > > + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), > + DEF_FIXED(".pll5_2", CLK_PLL5_2, CLK_PLL5, 1, 6), Suffix "_2" but divided by 6? Why do you need this clock? > + > + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), > + > DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), > DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), > DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), > @@ -73,6 +83,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), > DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), > > + DEF_FIXED(".pll5_2_div2", CLK_PLL5_DIV2, CLK_PLL5_2, 1, 2), ".pll5_div2" Figure 8.3 ("Clock System Diagram (2)") says the parent is CLK_PLL5? > + DEF_FIXED(".pll6_2_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), ".pll6_div2" > + > /* Core output clk */ > DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), > DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, > @@ -83,6 +96,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), > DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, > DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), > + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), > + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), > + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, > + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), OK. > }; > > static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { > diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h > index 148db5de253b..5202c0512483 100644 > --- a/drivers/clk/renesas/rzg2l-cpg.h > +++ b/drivers/clk/renesas/rzg2l-cpg.h > @@ -11,6 +11,7 @@ > > #define CPG_PL2_DDIV (0x204) > #define CPG_PL3A_DDIV (0x208) > +#define CPG_PL6_ETH_SSEL (0x418) > > /* n = 0/1/2 for PLL1/4/6 */ > #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) > @@ -24,6 +25,11 @@ > #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) > #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) > > +#define SEL_PLL_PACK(offset, bitpos, size) \ > + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) I think the addition of SEL_PLL_PACK() should be moved to [PATCH 02/18]. > + > +#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) > + > /** > * Definitions of CPG Core Clocks > * Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thanks for the feedback. > Subject: Re: [PATCH net-next 03/18] drivers: clk: renesas: r9a07g044-cpg: > Add ethernet clock sources > > Hi Biju, > > On Thu, Jul 22, 2021 at 4:14 PM Biju Das <biju.das.jz@bp.renesas.com> > wrote: > > Ethernet reference clock can be sourced from PLL5_2 or PLL6_2. Add > > support for ethernet source clock selection using SEL_PLL_6_2 mux. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > @@ -35,8 +35,10 @@ enum clk_ids { > > CLK_PLL3_DIV4, > > CLK_PLL4, > > CLK_PLL5, > > + CLK_PLL5_2, > > Why do you need this? We already have CLK_PLL5_DIV2? As per clock list HP =250 MHz. With PLL5_DIV2 the frequency, what we get is 3000 x 1/2 = 1500 MHz, which is incorrect There is some issue with HW manual. It is not clear. I have requested to fix those issue. Actually PLL5 generates 3 clk outputs (As per page 403 of manual) FOUTPOSTDIV= 3000 FOUT3 = 500 FOUT1PH0 = 1500 To match the clock list document and Figure 8.3 Clock system diagram for HP clock. This clock has to be FOUT3. FOUT3(second PLL5 clock source)* 1/2 =250 MHz(HP clock). On the HW manual, Divider name for PLL5 is mentioned as PLL_5_2_DIV12 and for PLL6 as PLL6_2_DIV2. > > > CLK_PLL5_DIV2, > > CLK_PLL6, > > + CLK_PLL6_DIV2, > > CLK_P1_DIV2, > > > > /* Module Clocks */ > > @@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = { > > {0, 0}, > > }; > > > > +/* Mux clock tables */ > > +static const char * const sel_pll6_2[] = { ".pll6_2_div2", > > +".pll5_2_div2" }; > > ".pll6_div2", ".pll5_div2" Basically PLL6 generates 2 clock outputs. That is the reason it is termed as PLL6_2 for second clock And pll5 generates 3 clock outputs and pll5_2(second clock source) is used for HP. To match the register definition, I will change this to ".pll6_2_div2" and ".pll5_2_div12". Is it ok? > > > + > > static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > > /* External Clock Inputs */ > > DEF_INPUT("extal", CLK_EXTAL), @@ -64,6 +69,11 @@ static const > > struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > > DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), > > DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), > > > > + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), > > + DEF_FIXED(".pll5_2", CLK_PLL5_2, CLK_PLL5, 1, 6), > > Suffix "_2" but divided by 6? > Why do you need this clock? To generate 500 MHz Clock, so that it can match with clock list document. > > > + > > + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), > > + > > DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), > > DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), > > DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), @@ > > -73,6 +83,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] > __initconst = { > > DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, > 1, 2), > > DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), > > > > + DEF_FIXED(".pll5_2_div2", CLK_PLL5_DIV2, CLK_PLL5_2, 1, 2), > > ".pll5_div2" > Figure 8.3 ("Clock System Diagram (2)") says the parent is CLK_PLL5? There is some issue in HW manual. Actually parent is second clock out from PLL5. See page 403. > > > + DEF_FIXED(".pll6_2_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), > > ".pll6_div2" > > > + > > /* Core output clk */ > > DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), > > DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, @@ > > -83,6 +96,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] > __initconst = { > > DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), > > DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, > > DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), > > + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), > > + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), > > + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, > > + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, > > + CLK_MUX_HIWORD_MASK), > > OK. > > > }; > > > > static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { diff --git > > a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h > > index 148db5de253b..5202c0512483 100644 > > --- a/drivers/clk/renesas/rzg2l-cpg.h > > +++ b/drivers/clk/renesas/rzg2l-cpg.h > > @@ -11,6 +11,7 @@ > > > > #define CPG_PL2_DDIV (0x204) > > #define CPG_PL3A_DDIV (0x208) > > +#define CPG_PL6_ETH_SSEL (0x418) > > > > /* n = 0/1/2 for PLL1/4/6 */ > > #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) > > @@ -24,6 +25,11 @@ > > #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) > > #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) > > > > +#define SEL_PLL_PACK(offset, bitpos, size) \ > > + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) > > I think the addition of SEL_PLL_PACK() should be moved to [PATCH 02/18]. > OK. Regards, Biju > > + > > +#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) > > + > > /** > > * Definitions of CPG Core Clocks > > * > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux- > m68k.org > > In personal conversations with technical people, I call myself a hacker. > But when I'm talking to journalists I just say "programmer" or something > like that. > -- Linus Torvalds
Hi Biju, On Mon, Jul 26, 2021 at 1:43 PM Biju Das <biju.das.jz@bp.renesas.com> wrote: > > Subject: Re: [PATCH net-next 03/18] drivers: clk: renesas: r9a07g044-cpg: > > Add ethernet clock sources > > On Thu, Jul 22, 2021 at 4:14 PM Biju Das <biju.das.jz@bp.renesas.com> > > wrote: > > > Ethernet reference clock can be sourced from PLL5_2 or PLL6_2. Add > > > support for ethernet source clock selection using SEL_PLL_6_2 mux. > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Thanks for your patch! > > > > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > > @@ -35,8 +35,10 @@ enum clk_ids { > > > CLK_PLL3_DIV4, > > > CLK_PLL4, > > > CLK_PLL5, > > > + CLK_PLL5_2, > > > > Why do you need this? We already have CLK_PLL5_DIV2? > > As per clock list HP =250 MHz. > > With PLL5_DIV2 the frequency, what we get is 3000 x 1/2 = 1500 MHz, which is incorrect > > There is some issue with HW manual. It is not clear. I have requested to fix those issue. > > Actually PLL5 generates 3 clk outputs (As per page 403 of manual) > > FOUTPOSTDIV= 3000 > FOUT3 = 500 > FOUT1PH0 = 1500 > > To match the clock list document and Figure 8.3 Clock system diagram for HP clock. > This clock has to be FOUT3. > > FOUT3(second PLL5 clock source)* 1/2 =250 MHz(HP clock). > > On the HW manual, Divider name for PLL5 is mentioned as PLL_5_2_DIV12 and for PLL6 as PLL6_2_DIV2. > > > > > > CLK_PLL5_DIV2, > > > CLK_PLL6, > > > + CLK_PLL6_DIV2, > > > CLK_P1_DIV2, > > > > > > /* Module Clocks */ > > > @@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = { > > > {0, 0}, > > > }; > > > > > > +/* Mux clock tables */ > > > +static const char * const sel_pll6_2[] = { ".pll6_2_div2", > > > +".pll5_2_div2" }; > > > > ".pll6_div2", ".pll5_div2" > > Basically PLL6 generates 2 clock outputs. That is the reason it is termed as PLL6_2 for second clock > And pll5 generates 3 clock outputs and pll5_2(second clock source) is used for HP. > > To match the register definition, I will change this to ".pll6_2_div2" and ".pll5_2_div12". Is it ok? OK, thanks for the explanation! Gr{oetje,eeting}s, Geert
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 9e9e8fb6d00d..c78bea2f6ea8 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -35,8 +35,10 @@ enum clk_ids { CLK_PLL3_DIV4, CLK_PLL4, CLK_PLL5, + CLK_PLL5_2, CLK_PLL5_DIV2, CLK_PLL6, + CLK_PLL6_DIV2, CLK_P1_DIV2, /* Module Clocks */ @@ -53,6 +55,9 @@ static const struct clk_div_table dtable_1_32[] = { {0, 0}, }; +/* Mux clock tables */ +static const char * const sel_pll6_2[] = { ".pll6_2_div2", ".pll5_2_div2" }; + static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), @@ -64,6 +69,11 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 133, 2), DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 133, 2), + DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1), + DEF_FIXED(".pll5_2", CLK_PLL5_2, CLK_PLL5, 1, 6), + + DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6), + DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2), DEF_FIXED(".pll2_div16", CLK_PLL2_DIV16, CLK_PLL2, 1, 16), DEF_FIXED(".pll2_div20", CLK_PLL2_DIV20, CLK_PLL2, 1, 20), @@ -73,6 +83,9 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), DEF_FIXED(".pll3_div4", CLK_PLL3_DIV4, CLK_PLL3, 1, 4), + DEF_FIXED(".pll5_2_div2", CLK_PLL5_DIV2, CLK_PLL5_2, 1, 2), + DEF_FIXED(".pll6_2_div2", CLK_PLL6_DIV2, CLK_PLL6, 1, 2), + /* Core output clk */ DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, @@ -83,6 +96,10 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2), DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), + DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), + DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), + DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, + sel_pll6_2, ARRAY_SIZE(sel_pll6_2), 0, CLK_MUX_HIWORD_MASK), }; static struct rzg2l_mod_clk r9a07g044_mod_clks[] = { diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h index 148db5de253b..5202c0512483 100644 --- a/drivers/clk/renesas/rzg2l-cpg.h +++ b/drivers/clk/renesas/rzg2l-cpg.h @@ -11,6 +11,7 @@ #define CPG_PL2_DDIV (0x204) #define CPG_PL3A_DDIV (0x208) +#define CPG_PL6_ETH_SSEL (0x418) /* n = 0/1/2 for PLL1/4/6 */ #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) @@ -24,6 +25,11 @@ #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) +#define SEL_PLL_PACK(offset, bitpos, size) \ + (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) + +#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) + /** * Definitions of CPG Core Clocks *