| Message ID | 20210923140813.13541-9-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add Gigabit Ethernet driver support | expand |
On 9/23/21 5:08 PM, Biju Das wrote: > E-MAC on RZ/G2L supports MII/RGMII selection. Add a > mii_rgmii_selection feature bit to struct ravb_hw_info > to support this for RZ/G2L. > Currently only selecting RGMII is supported. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > drivers/net/ethernet/renesas/ravb.h | 17 +++++++++++++++++ > drivers/net/ethernet/renesas/ravb_main.c | 6 ++++++ > 2 files changed, 23 insertions(+) > > diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h > index bce480fadb91..dfaf3121da44 100644 > --- a/drivers/net/ethernet/renesas/ravb.h > +++ b/drivers/net/ethernet/renesas/ravb.h [...] > @@ -951,6 +953,20 @@ enum RAVB_QUEUE { > RAVB_NC, /* Network Control Queue */ > }; > > +enum CXR31_BIT { > + CXR31_SEL_LINK0 = 0x00000001, > + CXR31_SEL_LINK1 = 0x00000008, > +}; > + > +enum CXR35_BIT { > + CXR35_SEL_MODIN = 0x00000100, > +}; > + > +enum CSR0_BIT { > + CSR0_TPE = 0x00000010, > + CSR0_RPE = 0x00000020, > +}; I don't see those used? What is CSR0? [...] > @@ -1008,6 +1024,7 @@ struct ravb_hw_info { > unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ > unsigned multi_tsrq:1; /* AVB-DMAC has MULTI TSRQ */ > unsigned magic_pkt:1; /* E-MAC supports magic packet detection */ > + unsigned mii_rgmii_selection:1; /* E-MAC supports mii/rgmii selection */ Perhaps just 'mii_rgmii_sel'? [...] > diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c > index 529364d8f7fb..5d18681582b9 100644 > --- a/drivers/net/ethernet/renesas/ravb_main.c > +++ b/drivers/net/ethernet/renesas/ravb_main.c [...] > @@ -1173,6 +1174,10 @@ static int ravb_phy_init(struct net_device *ndev) > netdev_info(ndev, "limited PHY to 100Mbit/s\n"); > } > > + if (info->mii_rgmii_selection && > + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) Not MII? > + ravb_write(ndev, ravb_read(ndev, CXR35) | CXR35_SEL_MODIN, CXR35); We have ravb_mnodify() for that... > + > /* 10BASE, Pause and Asym Pause is not supported */ > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); > @@ -2132,6 +2137,7 @@ static const struct ravb_hw_info rgeth_hw_info = { > .aligned_tx = 1, > .tx_counters = 1, > .no_gptp = 1, > + .mii_rgmii_selection = 1, I don't see where we handle MII? [...] MBR, Sergey
Hi Sergei, Thanks for the feedback. > Subject: Re: [RFC/PATCH 08/18] ravb: Add mii_rgmii_selection to struct > ravb_hw_info > > On 9/23/21 5:08 PM, Biju Das wrote: > > > E-MAC on RZ/G2L supports MII/RGMII selection. Add a > > mii_rgmii_selection feature bit to struct ravb_hw_info to support this > > for RZ/G2L. > > Currently only selecting RGMII is supported. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > drivers/net/ethernet/renesas/ravb.h | 17 +++++++++++++++++ > > drivers/net/ethernet/renesas/ravb_main.c | 6 ++++++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/drivers/net/ethernet/renesas/ravb.h > > b/drivers/net/ethernet/renesas/ravb.h > > index bce480fadb91..dfaf3121da44 100644 > > --- a/drivers/net/ethernet/renesas/ravb.h > > +++ b/drivers/net/ethernet/renesas/ravb.h > [...] > > @@ -951,6 +953,20 @@ enum RAVB_QUEUE { > > RAVB_NC, /* Network Control Queue */ > > }; > > > > +enum CXR31_BIT { > > + CXR31_SEL_LINK0 = 0x00000001, > > + CXR31_SEL_LINK1 = 0x00000008, > > +}; > > + > > +enum CXR35_BIT { > > + CXR35_SEL_MODIN = 0x00000100, > > +}; > > + > > +enum CSR0_BIT { > > + CSR0_TPE = 0x00000010, > > + CSR0_RPE = 0x00000020, > > +}; > > I don't see those used? What is CSR0? OK, This has to be part of later patch for emac_init. CSR is checksum operating mode register in TOE. > > [...] > > @@ -1008,6 +1024,7 @@ struct ravb_hw_info { > > unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in > config mode */ > > unsigned multi_tsrq:1; /* AVB-DMAC has MULTI TSRQ */ > > unsigned magic_pkt:1; /* E-MAC supports magic packet > detection */ > > + unsigned mii_rgmii_selection:1; /* E-MAC supports mii/rgmii > selection */ > > Perhaps just 'mii_rgmii_sel'? OK. > > [...] > > diff --git a/drivers/net/ethernet/renesas/ravb_main.c > > b/drivers/net/ethernet/renesas/ravb_main.c > > index 529364d8f7fb..5d18681582b9 100644 > > --- a/drivers/net/ethernet/renesas/ravb_main.c > > +++ b/drivers/net/ethernet/renesas/ravb_main.c > [...] > > @@ -1173,6 +1174,10 @@ static int ravb_phy_init(struct net_device *ndev) > > netdev_info(ndev, "limited PHY to 100Mbit/s\n"); > > } > > > > + if (info->mii_rgmii_selection && > > + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) > > Not MII? Currently only RGMII supported, see the commit message. > > > + ravb_write(ndev, ravb_read(ndev, CXR35) | CXR35_SEL_MODIN, > CXR35); > > We have ravb_mnodify() for that... > > > + > > /* 10BASE, Pause and Asym Pause is not supported */ > > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); > > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); > > @@ -2132,6 +2137,7 @@ static const struct ravb_hw_info rgeth_hw_info = { > > .aligned_tx = 1, > > .tx_counters = 1, > > .no_gptp = 1, > > + .mii_rgmii_selection = 1, > > I don't see where we handle MII? See the commit message. "Currently only selecting RGMII is supported." We have a plan to support this at later. Regards, Biju > > [...] > > MBR, Sergey
Hi Sergei, > Subject: RE: [RFC/PATCH 08/18] ravb: Add mii_rgmii_selection to struct > ravb_hw_info > > Hi Sergei, > > Thanks for the feedback. > > > Subject: Re: [RFC/PATCH 08/18] ravb: Add mii_rgmii_selection to struct > > ravb_hw_info > > > > On 9/23/21 5:08 PM, Biju Das wrote: > > > > > E-MAC on RZ/G2L supports MII/RGMII selection. Add a > > > mii_rgmii_selection feature bit to struct ravb_hw_info to support > > > this for RZ/G2L. > > > Currently only selecting RGMII is supported. > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- > > > drivers/net/ethernet/renesas/ravb.h | 17 +++++++++++++++++ > > > drivers/net/ethernet/renesas/ravb_main.c | 6 ++++++ > > > 2 files changed, 23 insertions(+) > > > > > > diff --git a/drivers/net/ethernet/renesas/ravb.h > > > b/drivers/net/ethernet/renesas/ravb.h > > > index bce480fadb91..dfaf3121da44 100644 > > > --- a/drivers/net/ethernet/renesas/ravb.h > > > +++ b/drivers/net/ethernet/renesas/ravb.h > > [...] > > > @@ -951,6 +953,20 @@ enum RAVB_QUEUE { > > > RAVB_NC, /* Network Control Queue */ > > > }; > > > > > > +enum CXR31_BIT { > > > + CXR31_SEL_LINK0 = 0x00000001, > > > + CXR31_SEL_LINK1 = 0x00000008, > > > +}; > > > + > > > +enum CXR35_BIT { > > > + CXR35_SEL_MODIN = 0x00000100, > > > +}; > > > + > > > +enum CSR0_BIT { > > > + CSR0_TPE = 0x00000010, > > > + CSR0_RPE = 0x00000020, > > > +}; > > > > I don't see those used? What is CSR0? > > OK, This has to be part of later patch for emac_init. CSR is checksum > operating mode register in TOE. > > > > > [...] > > > @@ -1008,6 +1024,7 @@ struct ravb_hw_info { > > > unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in > > config mode */ > > > unsigned multi_tsrq:1; /* AVB-DMAC has MULTI TSRQ */ > > > unsigned magic_pkt:1; /* E-MAC supports magic packet > > detection */ > > > + unsigned mii_rgmii_selection:1; /* E-MAC supports mii/rgmii > > selection */ > > > > Perhaps just 'mii_rgmii_sel'? > OK. > > > > > [...] > > > diff --git a/drivers/net/ethernet/renesas/ravb_main.c > > > b/drivers/net/ethernet/renesas/ravb_main.c > > > index 529364d8f7fb..5d18681582b9 100644 > > > --- a/drivers/net/ethernet/renesas/ravb_main.c > > > +++ b/drivers/net/ethernet/renesas/ravb_main.c > > [...] > > > @@ -1173,6 +1174,10 @@ static int ravb_phy_init(struct net_device > *ndev) > > > netdev_info(ndev, "limited PHY to 100Mbit/s\n"); > > > } > > > > > > + if (info->mii_rgmii_selection && > > > + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) > > > > Not MII? > > Currently only RGMII supported, see the commit message. > > > > > + ravb_write(ndev, ravb_read(ndev, CXR35) | CXR35_SEL_MODIN, > > CXR35); > > > > We have ravb_mnodify() for that... > > > > > + > > > /* 10BASE, Pause and Asym Pause is not supported */ > > > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); > > > phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); > > > @@ -2132,6 +2137,7 @@ static const struct ravb_hw_info rgeth_hw_info = > { > > > .aligned_tx = 1, > > > .tx_counters = 1, > > > .no_gptp = 1, > > > + .mii_rgmii_selection = 1, > > > > I don't see where we handle MII? > > See the commit message. "Currently only selecting RGMII is supported." > We have a plan to support this at later. > I have prepared a patch with "mii_rgmii_sel", will send next revision soon. Regards, Biju
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index bce480fadb91..dfaf3121da44 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -189,6 +189,8 @@ enum ravb_reg { PIR = 0x0520, PSR = 0x0528, PIPR = 0x052c, + CXR31 = 0x0530, /* Documented for RZ/G2L only */ + CXR35 = 0x0540, /* Documented for RZ/G2L only */ MPR = 0x0558, PFTCR = 0x055c, PFRCR = 0x0560, @@ -951,6 +953,20 @@ enum RAVB_QUEUE { RAVB_NC, /* Network Control Queue */ }; +enum CXR31_BIT { + CXR31_SEL_LINK0 = 0x00000001, + CXR31_SEL_LINK1 = 0x00000008, +}; + +enum CXR35_BIT { + CXR35_SEL_MODIN = 0x00000100, +}; + +enum CSR0_BIT { + CSR0_TPE = 0x00000010, + CSR0_RPE = 0x00000020, +}; + #define DBAT_ENTRY_NUM 22 #define RX_QUEUE_OFFSET 4 #define NUM_RX_QUEUE 2 @@ -1008,6 +1024,7 @@ struct ravb_hw_info { unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */ unsigned multi_tsrq:1; /* AVB-DMAC has MULTI TSRQ */ unsigned magic_pkt:1; /* E-MAC supports magic packet detection */ + unsigned mii_rgmii_selection:1; /* E-MAC supports mii/rgmii selection */ }; struct ravb_private { diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index 529364d8f7fb..5d18681582b9 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -1128,6 +1128,7 @@ static int ravb_phy_init(struct net_device *ndev) { struct device_node *np = ndev->dev.parent->of_node; struct ravb_private *priv = netdev_priv(ndev); + const struct ravb_hw_info *info = priv->info; struct phy_device *phydev; struct device_node *pn; phy_interface_t iface; @@ -1173,6 +1174,10 @@ static int ravb_phy_init(struct net_device *ndev) netdev_info(ndev, "limited PHY to 100Mbit/s\n"); } + if (info->mii_rgmii_selection && + priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) + ravb_write(ndev, ravb_read(ndev, CXR35) | CXR35_SEL_MODIN, CXR35); + /* 10BASE, Pause and Asym Pause is not supported */ phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); @@ -2132,6 +2137,7 @@ static const struct ravb_hw_info rgeth_hw_info = { .aligned_tx = 1, .tx_counters = 1, .no_gptp = 1, + .mii_rgmii_selection = 1, }; static const struct of_device_id ravb_match_table[] = {
E-MAC on RZ/G2L supports MII/RGMII selection. Add a mii_rgmii_selection feature bit to struct ravb_hw_info to support this for RZ/G2L. Currently only selecting RGMII is supported. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- drivers/net/ethernet/renesas/ravb.h | 17 +++++++++++++++++ drivers/net/ethernet/renesas/ravb_main.c | 6 ++++++ 2 files changed, 23 insertions(+)